INTERPOSER FOR INTEGRATED CIRCUIT CHIP PACKAGE

• US 20150194413A1
• Filed: 01/06/2014
• Published: 07/09/2015
• Est. Priority Date: 01/06/2014
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: LEE, Michael, YAMAMOTO, Takuji
• Granted Patent: US 9,496,248 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02B 6/4249 comprising arrays of active devices and fibres
• CPC Class Codes: G02B 6/4268 Cooling of semiconductor devices H01L23/24; of electric apparatus H05K7/20; of instruments G12B15/00
• CPC Class Codes: G02B 6/4274 Electrical aspects G02B6/4263 and G02B6/4265 take precedence
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

An interposer for an electronic circuit chip package may include a substrate, a recess, first conductive vias, and second conductive vias. The substrate may have a first surface, a second surface substantially parallel to and opposite the first surface, a third surface substantially parallel to the first surface and the second surface, and an orthogonal surface that is substantially orthogonal to and intersects the first surface and the third surface. The recess may be formed in the substrate and defined by the third surface and the orthogonal surface. The first conductive vias may pass from the second surface to the first surface. The second conductive vias may pass from the second surface to the third surface.

Claims

1. An interposer for an electronic circuit chip package, the interposer comprising:

a substrate having a first surface, a second surface substantially parallel to and opposite the first surface, a third surface substantially parallel to the first surface and the second surface, and an orthogonal surface that is substantially orthogonal to and intersects the first surface and the third surface;

a recess formed in the substrate and defined by the third surface and the orthogonal surface;

a first plurality of conductive vias that pass from the second surface to the first surface; and

a second plurality of conductive vias that pass from the second surface to the third surface.

2. The interposer of claim 1, wherein the substrate comprises a metal, a dielectric, or a semiconductor.

3. The interposer of claim 1, wherein:

the first plurality of conductive vias is configured to electrically couple a first chip mounted to the second surface to a package substrate coupled to the first surface; and

the second plurality of conductive vias is configured to electrically couple the first chip mounted to the second surface to a second chip mounted to the third surface within the recess.

4. The interposer of claim 3, further comprising a side piece defining a side of the recess that is opposite the orthogonal surface, wherein the side piece defines a plurality of through channels, each configured to receive an elongate transmission medium extending from the second chip out of the recess through a corresponding one of the plurality of through channels in a direction substantially parallel to the third surface.

5. The interposer of claim 4, wherein the substrate further includes an extension extending from the third surface in a direction away from the second surface, the extension cooperating with the side piece to define the through channels.

6. The interposer of claim 4, further comprising a baffle plate configured to cooperate with the substrate and the side piece to enclose the second chip within the recess.

7. A method comprising:

forming an interposer of an electronic circuit chip package, wherein forming the interposer includes;

forming a substrate having a first surface and a second surface substantially parallel to and opposite the first surface;

forming a plurality of conductive vias in the substrate;

forming a recess in the substrate, the recess defined by a third surface of the substrate substantially parallel to the first surface and by an orthogonal surface that is substantially orthogonal to and intersects the first surface and the third surface, wherein a first of the plurality of conductive vias passes from the second surface to the third surface; and

forming a first bond pad on the third surface that is electrically coupled to the first of the plurality of conductive vias.

8. The method of claim 7, wherein forming the recess in the substrate includes removing, from the second surface to the third surface, a portion of the substrate and a portion of the first of the plurality of conductive vias.

9. The method of claim 8, wherein the portion of the substrate and the portion of the first of the plurality of conductive vias are removed substantially simultaneously or in sequence.

10. The method of claim 7, wherein the plurality of conductive vias includes a first plurality of conductive vias and a second plurality of conductive vias, each of the first plurality of conductive vias passes from the first surface to the second surface, the second plurality of conductive vias includes the first of the plurality of conductive vias, and each of the second plurality of conductive vias passes from the first surface to the third surface, the method further comprising:

mounting a first chip to the second surface of the substrate;

mounting a second chip to the third surface of the substrate within the recess such that the second plurality of conductive vias electrically couple the first chip to the second chip; and

coupling the first surface of the substrate to a package substrate of the IC chip package such that the first plurality of conductive vias electrically couple the first chip to the package substrate.

11. The method of claim 10, wherein the recess is further defined by an extension of the substrate extending from the third surface in a direction away from the second surface, and wherein forming the interposer further includes:

forming a side piece that cooperates with the extension of the substrate to define a side of the recess that is opposite the orthogonal surface;

forming first notches in a surface of the extension that faces the side piece;

forming second notches in a surface of the side piece that faces the extension;

communicatively coupling elongate transmission media to the second chip, the elongate transmission media extending out of the recess in a direction substantially parallel to the third surface; and

securing the side piece relative to the extension such that the first notches and the second notches form through channels through which the elongate transmission media extend out of the recess.

12. The method of claim 11, wherein forming the interposer further includes:

forming a baffle plate;

forming a first ledge in the substrate where the orthogonal surface and the first surface intersect;

forming a second ledge in the side piece, wherein the first ledge and the second ledge define a baffle plate seat; and

mounting the baffle plate in the baffle plate seat, wherein the baffle plate, the substrate, and the side piece cooperate to enclose the second chip within the recess.

13. The method of claim 12, further comprising:

forming a fluid channel through at least one of the substrate, the side piece, and the baffle plate; and

coupling a fluid guide to the fluid channel, wherein the fluid guide is configured to carry fluid to the recess, from the recess, or both to and from the recess through the fluid channel.

14. The method of claim 7, wherein the first bond pad is formed on the third surface by:

forming an electrically conductive layer on the second surface that is electrically coupled to the first of the plurality of conductive vias;

placing the substrate and electrically conductive layer in an electrolyte bath;

applying an electric current to the electrically conductive layer; and

depositing the first bond pad on the third surface such that the first bond pad is electrically coupled to the first of the plurality of conductive vias.

15. An electronic circuit chip package comprising:

a package substrate;

an interposer including a substrate having a first surface and a second surface substantially parallel to and opposite the first surface, wherein the first surface is coupled to the package substrate;

a first chip mounted to the second surface of the substrate, the substrate including a first plurality of conductive vias that electrically couple the first chip mounted to the second surface to the package substrate coupled to the first surface; and

a second chip mounted in a recess to a third surface of the substrate that faces the substrate package, the recess defined by the third surface that is substantially parallel to the first surface and by an orthogonal surface of the substrate that is substantially orthogonal to and intersects the first surface and the third surface, the substrate including a second plurality of conductive vias that electrically couple the first chip mounted to the first surface to the second chip mounted to the third surface.

16. The electronic circuit chip package of claim 15, wherein the first chip comprises a central processing unit (CPU) and the second chip comprises a photonic integrated circuit (PIC).

17. The electronic circuit chip package of claim 15, further comprising a heat sink coupled to a backside of the first chip that is substantially parallel to and opposite a front side of the first chip, the front side of the first chip coupled to the second surface of the substrate of the interposer.

18. The electronic circuit chip package of claim 15, wherein the second plurality of conductive vias electrically couple a driver of the first chip to the second chip.

19. The electronic circuit chip package of claim 15, wherein the recess of the interposer is enclosed by an enclosure made at least partially of the substrate and wherein the interposer defines at least one fluid channel that passes through the enclosure, the electronic circuit chip package further comprising:

a fluid reservoir; and

a fluid guide coupled between the fluid channel and the fluid reservoir, wherein the fluid guide is configured to carry fluid between the fluid reservoir and the recess.

20. The electronic circuit chip package of claim 19, further comprising a plurality of elongate transmission media communicatively coupled to the second chip and extending out of the recess through the enclosure in a direction substantially parallel to the third surface.