SINGLE-CHIP FIELD EFFECT TRANSISTOR (FET) SWITCH WITH SILICON GERMANIUM (SiGe) POWER AMPLIFIER AND METHODS OF FORMING

• US 20150194416A1
• Filed: 01/03/2014
• Published: 07/09/2015
• Est. Priority Date: 01/03/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dunn, James S., Gross, Blaine J., Liu, Qizhi, Slinkman, James A., Cheng, Peng
• Granted Patent: US 9,653,477 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.

Claims

1. A method comprising:

forming a first set of openings in a precursor structure having;

a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide;

a silicon germanium (SiGe) layer overlying the silicon substrate;

a silicon layer overlying the SiGe layer;

a second oxide overlying the silicon layer; and

a sacrificial layer overlying the second oxide,

wherein the first set of openings each expose the silicon substrate;

undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings;

passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and

at least partially filling each trench with a dielectric.

2. The method of claim 1, wherein the dielectric includes a third oxide.

3. The method of claim 1, further comprising removing the sacrificial layer.

4. The method of claim 3, wherein the removing of the sacrificial layer includes selectively etching the sacrificial layer to expose the second oxide layer.

5. The method of claim 4, further comprising forming a gate and spacers over the second oxide layer;

6. The method of claim 5, further comprising:

forming salicide regions in the silicon layer; and

forming contacts to the salicide regions and the gate.

7. The method of claim 5, wherein the forming of the gate and the spacers is performed prior to the forming of the first set of openings in the precursor structure.

8. The method of claim 1, further comprising removing the second oxide layer to expose the silicon layer on top of the SiGe layer.

9. The method of claim 8, further comprising re-growing a gate oxide over the exposed silicon layer on top of the SiGe layer.

10. The method of claim 1, further comprising performing a selective etch on the SiGe layer after the undercut etching to remove the SiGe layer along a bottom surface of the silicon layer within each trench.

11. The method of claim 1, wherein the forming of the first opening includes forming a resist layer over the sacrificial layer and etching through the sacrificial layer, the second oxide layer, the silicon layer and the SiGe layer to expose the silicon substrate.

12. The method of claim 1, wherein the at least partially filling of each trench with the dielectric includes filling a portion of each trench to leave an air gap in each trench, the air gap surrounded by the dielectric.

13. A method comprising:

forming a first set of openings in a precursor structure having;

a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide;

a silicon germanium (SiGe) layer overlying the silicon substrate;

a silicon layer overlying the SiGe layer;

a second oxide overlying the silicon layer; and

a sacrificial layer overlying the second oxide,

wherein the first set of openings each expose the silicon substrate;

undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings;

passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings;

at least partially filling each trench with a dielectric to form an air gap within the trench, the air gap surrounded by the dielectric; and

selectively etching the sacrificial layer to expose the second oxide layer.

14. The method of claim 13, further comprising:

forming a gate and spacers over the second oxide layer;

forming salicide regions in the silicon layer; and

forming contacts to the salicide regions and the gate.

15. The method of claim 13, further comprising performing a selective etch on the SiGe layer after the undercut etching to remove the SiGe layer along a bottom surface of the silicon layer within each trench.

16. The method of claim 13, wherein the forming of the first opening includes forming a resist layer over the sacrificial layer and etching through the sacrificial layer, the second oxide layer, the silicon layer and the SiGe layer to expose the silicon substrate.

17. The method of claim 13, wherein the at least partially filling of each trench with the dielectric includes filling a portion of each trench to leave an air gap in each trench, the air gap surrounded by the dielectric.

18. A field effect transistor (FET) comprising:

a silicon substrate including a set of trenches;

a first oxide abutting the silicon substrate;

a silicon germanium (SiGe) layer overlying the silicon substrate;

a silicon layer overlying the SiGe layer;

a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions;

a gate structure overlying the second oxide between adjacent salicide regions; and

a first contact contacting the gate structure;

a second contact contacting one of the salicide regions;

a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and

an air gap in each of the set of trenches, the air gap surrounded by the third oxide.

19. The FET of claim 18, wherein the set of trenches is oriented in a direction perpendicular to a direction of the gate structure, or parallel to a direction of the gate structure.

20. The FET of claim 18, wherein the set of trenches is oriented in a direction perpendicular to a direction of the gate structure, and wherein the FET is stackable with another substantially similar FET structure having a set of trenches oriented in a direction perpendicular to a direction of a gate structure in the similar FET structure.

21. An integrated circuit (IC) layout comprising:

a plurality of cells including at least one of a switching chip or a power amplifier chip, wherein the at least one of the switching chip or the power amplifier chip includes a field effect transistor (FET) structure having;

a silicon substrate including a set of trenches;

a first oxide abutting the silicon substrate;

a silicon germanium (SiGe) layer overlying the silicon substrate;

a silicon layer overlying the SiGe layer;

a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions;

a gate structure overlying the second oxide between adjacent salicide regions; and

a first contact contacting the gate structure;

a second contact contacting one of the salicide regions;

a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and

an air gap in each of the set of trenches, the air gap surrounded by the third oxide.

22. The IC layout of claim 21, wherein the plurality of cells includes a cell having a plurality of switching chips, and wherein all of the plurality of switching chips in the cell have a same number of stacked FET structures.

23. The IC layout of claim 21, wherein the set of trenches in the FET is oriented in a direction perpendicular to a direction of the gate structure, or parallel to a direction of the gate structure.