Method of Producing a Vertically Inhomogeneous Platinum or Gold Distribution in a Semiconductor Substrate and in a Semiconductor Device

• US 20150194491A1
• Filed: 03/21/2015
• Published: 07/09/2015
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Schmidt, Gerhard, Bauer, Josef-Georg
• Granted Patent: US 9,263,529 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/322 to modify their internal properties, e.g. to produce internal imperfections
• CPC Class Codes: H01L 21/3221 of silicon bodies, e.g. for gettering
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.

Claims

1. A semiconductor device having a thickness L comprising:

a p-doped region;

an n-doped region; and

a vertically inhomogeneous heavy metal doping profile comprising a first heavy metal doping concentration greater than C1 across a first depth region of a thickness greater than L/6 and a second heavy metal doping concentration smaller than C2 across a second depth region of a thickness greater than L/6, wherein C1>

3×

C2.

2. The semiconductor device according to claim 1, wherein the first depth region of a thickness greater than L/4 comprises a heavy metal doping concentration greater than C1 and a second depth region of a thickness greater than L/4 a second heavy metal doping concentration smaller than C2, wherein C1>

4×

C2, and wherein the second depth region with a platinum doping concentration C2 comprises a thickness of 50 μ

m to 600 μ

m.

3. The semiconductor device according to claim 1, wherein the first depth region of a thickness greater than L/6 comprises a first heavy metal doping concentration greater than C1 and a second depth region of a thickness greater than L/6 a second heavy metal doping concentration smaller than C2, wherein C1>

10×

C2, and wherein the second depth region with a platinum doping concentration C2 comprises a thickness of 50 μ

m to 600 μ

m.

4. The semiconductor device according to claim 1, wherein the semiconductor device comprises a thickness of L<

200 μ

m.

5. The semiconductor device according to claim 1, wherein the heavy metal doping profile between the first depth region and the second depth region comprises a gradient with a decrease in the heavy metal doping concentration by at least a power of ten per 100 μ

m of semiconductor diode thickness L.

6. The semiconductor device according to claim 1, wherein the semiconductor device is a diode.

7. The semiconductor device according to claim 1, wherein the semiconductor device is an insulated-gate bipolar transistor (IGBT).

8. The semiconductor device according to claim 1, wherein the semiconductor device is a reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with an integrated diode.

9. The semiconductor device according to claim 1, wherein the semiconductor device is a double-diffused metal-oxide semiconductor (DMOS) transistor.

10. A semiconductor substrate comprising:

a semiconductor substrate of a thickness L, with a first and a second surface opposite the first surface, with a vertically inhomogeneous platinum or gold doping profile comprising a first platinum or gold doping concentration greater than C1 across a first depth region of a thickness greater than L/6 and a second platinum or gold doping concentration smaller than C2 across a second depth region of a thickness greater than L/6, wherein C1>

4×

C2.