MASKING CIRCUIT AND TIME-TO-DIGITAL CONVERTER COMPRISING THE SAME

• US 20150194971A1
• Filed: 01/07/2014
• Published: 07/09/2015
• Est. Priority Date: 01/07/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSAI, TSUNG-HSIEN
• Granted Patent: US 9,270,290 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03L 2207/18 Temporarily disabling, deactivating or stopping the frequency counter or divider
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00

Abstract

A time-to-digital converter (TDC) comprises a TDC core and a masking circuit. The TDC core is configured to detect phase difference between a reference signal and a controlled signal. The masking circuit is configured to generate a mask signal based on the reference signal, the controlled signal, and a command signal including information of a predetermined value associated with the reference signal and the controlled signal. The mask signal is used to mask a portion of pulses of the controlled signal from entering the TDC core during detection of phase difference.

Claims

1. A masking circuit for a time-to-digital converter (TDC), the masking circuit comprising:

a reset circuit configured to generate a reset signal based on a reference signal and a controlled signal, the reference signal and the controlled signal to be sent to the TDC for detection of phase difference;

a counter configured to count to a predetermined value associated with the reference signal and the controlled signal, and configured to be reset to an initial value in response to the reset signal; and

a comparator configured to compare a count from the counter and the predetermined value, and to generate a mask signal when a count from the counter equals the predetermined value, the mask signal masking a portion of pulses of the controlled signal from entering the TDC.

2. The masking circuit of claim 1, wherein the predetermined value is (FCW−

N), where FCW represents a frequency command word obtained by dividing the frequency of the controlled signal by the frequency of the reference signal, and N is a natural number that satisfies

PCKV×

N>

DTDC,

where PCKV represents the period of the controlled signal, and DTDC represents a delay to be introduced in the TDC if controlled signal enters the TDC without masking.

3. The masking circuit of claim 1, wherein the counter includes a selecting device configured to receive the mask signal as a control signal.

4. The masking circuit of claim 3, wherein the counter includes a latch device configured to generate a count at a data output in response to the reset signal.

5. The masking circuit of claim 4, wherein the counter includes a summing device configured to add an output from the selecting device and a count from the latch device.

6. The masking circuit of claim 5, wherein the counter includes a decision circuit between an output of the summing device and a data input of the latch device.

7. The masking circuit of claim 4, wherein the counter includes a decision circuit between an output of the reset circuit and a reset port of the latch device.

8. The masking circuit of claim 1, wherein the counter includes a first latch device and a second latch device, the first latch device being configured to serve as a frequency divider for the second latch device.

9. The masking circuit of claim 8, wherein the counter includes a decision circuit having an input coupled to an output of the reset circuit, and an output coupled to a reset port each of the first latch device and the second latch device.

10. The masking circuit of claim 1, wherein the masking signal having an active period determined by the predetermined value.

11. A time-to-digital converter (TDC), comprising:

a TDC core configured to detect phase difference between a reference signal and a controlled signal; and

a masking circuit configured to generate a mask signal based on the reference signal, the controlled signal, and a command signal including information of a predetermined value associated with the reference signal and the controlled signal, the mask signal masking a portion of pulses of the controlled signal from entering the TDC core.

12. The TDC of claim 11, wherein the predetermined value is (FCW−

N), where FCW represents a frequency command word obtained by dividing the frequency of the controlled signal by the frequency of the reference signal, and N is a natural number that satisfies

PCKV×

N>

DTDC,

where PCKV represents the period of the controlled signal, and DTDC represents a delay to be introduced in the TDC core if controlled signal enters the TDC core without masking.

13. The TDC of claim 11, wherein the masking circuit includes:

a reset circuit configured to generate a reset signal based on the reference signal and the controlled signal; and

a counter configured to count to the predetermined value, and to be reset to an initial value in response to the reset signal.

14. The TDC of claim 13, wherein the counter includes a selecting device configured to receive the mask signal as a control signal.

15. The TDC of claim 14, wherein the counter includes a latch device configured to generate a count at a data output in response to the reset signal.

16. The TDC of claim 15, wherein the counter includes a decision circuit between an output of the reset circuit and a data input of the latch device.

17. The TDC of claim 15, wherein the counter includes a decision circuit between an output of the reset circuit and a reset port of the latch device.

18. The TDC of claim 11, wherein the counter includes a first latch device and a second latch device, the first latch device being configured to serve as a frequency divider for the second latch device.

19. A method, comprising:

receiving a reference signal and a controlled signal for phase comparison;

determining a frequency command word, FCW, based on the frequency of the reference signal and the frequency of the controlled signal;

determining a number, N, based on the period of the controlled signal and a delay to be introduced if the entire controlled signal is used in the phase comparison;

generating a mask signal based on the frequency command word FCW and the value of N; and

masking a number of pulses of the controlled signal from the phase comparison with the mask signal.

20. The method of claim 19, wherein the frequency command word FCW is obtained by dividing the frequency of the controlled signal by the frequency of the reference signal, and N is a natural number that satisfies

PCKV×

N>

DTDC,

where PCKV represents the period of the controlled signal, and DTDC represents the delay.