PACKET PARSING ENGINE

• US 20150195384A1
• Filed: 01/08/2014
• Published: 07/09/2015
• Est. Priority Date: 01/08/2014
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Snyder, Wilson Parkhurst II, Katz, Daniel Adam, Ogale, Varada Ramesh
• Granted Patent: US 10,447,823 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A packet parsing engine comprises a DMEM configured to store packet data; one or more registers configured to store parsing instructions or parse results; and one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results. The engine may be one engine of a plurality of engines configured to access a shared memory, and the engine may be configured to receive data from the shared memory or to send data to the shared memory. The DMEM may be divided into subsections, and at least one of the one or more registers may be divided into subsections, and the subsections may be configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet.

Claims

1. A packet parsing engine comprising:

a DMEM configured to store packet data;

one or more registers configured to store parsing instructions or parse results; and

one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results.

2. The engine of claim 1, wherein the engine is one engine of a plurality of engines and wherein the plurality of engines are configured to access a shared memory, and wherein the engine is configured to receive data from the shared memory or to send data to the shared memory.

3. The engine of claim 1, wherein the DMEM is divided into two or more DMEM subsections, and at least one of the one or more registers is divided into two or more register subsections, each register subsection corresponding to a DMEM subsection, and wherein the subsections are configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet.

4. The engine of claim 3, wherein the DMEM and the registers are each divided into two subsections.

5. The engine of claim 1, wherein the engine is configured such that before parsing each packet data one or more register files for the one or more registers are initialized.

6. The engine of claim 5, wherein the one or more register files are initialized through the instructions.

7. The engine of claim 5, wherein the engine is one engine of a plurality of engines and wherein the plurality of engines are configured to access a shared memory, and wherein the one or more register files are initialized by receiving data from the shared memory.

8. The engine of claim 1, wherein the parsing instructions are wide 64 bits.

9. The engine of claim 1, wherein two or more of the DMEM, the one or more registers, and the one or more arithmetic logic units communicate via 16 bit data.

10. A method of parsing packet data by a packet parsing engine, wherein the engine includes a DMEM, one or more registers, and one or more arithmetic units (ALUs), the method comprising:

storing data for a packet in the DMEM;

storing parsing instructions in the one or more registers;

parsing, by the ALUs, packet data based on the parsing instructions and deriving parse results; and

storing parse results in the one or more registers.

11. The method of claim 10, wherein the engine is one engine of a plurality of engines, the method further comprising accessing a shared memory that is configured to be accessed by the plurality of engines, wherein the accessing includes receiving data from the shared memory or sending data to the shared memory.

12. The method of claim 10, wherein the DMEM is divided into two or more DMEM subsections, and at least one of the one or more registers is divided into two or more register subsections, each register subsection corresponding to a DMEM subsection, the method further comprising parsing packet data for a first packet by a DMEM subsection and its corresponding register subsection while one or more of other subsections load packed data or unload parse results for a second packet.

13. The method of claim 12, wherein the DMEM and the registers are each divided into two subsections.

14. The method of claim 10 further comprising initializing one or more register files for the one or more registers before parsing each packet data.

15. The method of claim 14, wherein the one or more register files are initialized through the instructions.

16. The method of claim 14, wherein the engine is one engine of a plurality of engines and wherein the plurality of engines are configured to access a shared memory, and wherein the one or more register files are initialized by receiving data from the shared memory.

17. The method of claim 10, wherein the parsing instructions are wide 64 bits.

18. The method of claim 10, further comprising sending communications among two or more of the DMEM, the one or more registers, and the one or more arithmetic logic units via 16 bit data.

19. A method of parsing packet data by a packet parsing engine, the method comprising:

setting a state of the engine to an idle state;

loading packet data to the engine and changing the state of the engine to an allocated state;

starting parsing the packet data and changing the state of the engine to a processing state; and

completing the parsing, unloading parse results, and setting the state of the engine to the idle state.

20. A non-transitory computer readable medium storing one or more programs, wherein the program, when executed by a packet parsing engine, causes the packet parsing engine to perform a method of parsing packet data, the method comprising:

setting a state of the engine to an idle state;

loading packet data to the engine and changing the state of the engine to an allocated state;

starting parsing the packet data and changing the state of the engine to a processing state; and

completing the parsing, unloading parse results, and setting the state of the engine to the idle state.