STATE-DEPENDENT CAPACITANCE ESTIMATION

• US 20150198657A1
• Filed: 01/16/2014
• Published: 07/16/2015
• Est. Priority Date: 01/16/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Coutts, Ryan Michael, Allam, Mohamed Waleed
• Granted Patent: US 9,638,743 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: H02J 1/00 Circuit arrangements for dc mains or dc distribution networks
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques for estimating state-dependent capacitance of a circuit are described herein. In one embodiment, a method for determining a circuit state for a circuit comprises determining a capacitance of the circuit for each one of a plurality of circuit states, and selecting one of the circuit states based on the determined capacitances.

Claims

1. A method for determining a circuit state for a circuit, comprising:

determining a capacitance of the circuit for each one of a plurality of circuit states; and

selecting one of the circuit states based on the determined capacitances.

2. The method of claim 1, wherein selecting one of the circuit states comprising selecting the circuit state corresponding to a lowest one of the determined capacitances.

3. The method of claim 1, wherein each circuit state corresponds to a different combination of active-device states and parasitic-capacitor states in the circuit.

4. The method of claim 1, further comprising placing the circuit in the selected circuit state while powering up the circuit.

5. The method of claim 1, wherein the circuit comprises a plurality of inputs, and the method further comprises determining a combination of input logic states for the inputs that places the circuit in the selected circuit state.

6. The method of claim 1, wherein determining the capacitance of the circuit for each one of the plurality of circuit states comprises:

determining a state for each one of a plurality of devices in the circuit;

determining a capacitance for each device based on the determined state for the device; and

summing the determined capacitances for the plurality of devices.

7. The method of claim 1, wherein determining the capacitance of the circuit for each one of the plurality of circuit states comprises:

determining a state for each one of plurality of parasitic capacitors in the circuit;

determining a capacitance for each parasitic capacitor based on the determined state for the parasitic capacitor; and

summing the determined capacitances for the plurality of parasitic capacitors.

8. An apparatus for placing a circuit in a circuit state, wherein the circuit comprises a plurality of inputs, the apparatus comprising:

a plurality of input drivers, wherein each of the input drivers is configured to drive a respective one of the plurality of inputs; and

an input controller configured to control the plurality of input drivers such that, during power up of the circuit, the input drivers drive the plurality of inputs according to a combination of input logic states that places the circuit in the circuit state;

wherein the circuit state is one of a plurality of circuit states corresponding to a plurality of different capacitances, and the circuit state corresponds to a lowest one of the plurality of capacitances.

9. The apparatus of claim 8, wherein the input controller is configured to turn off the input drivers after power up of the circuit.

10. The apparatus of claim 8, wherein each of the plurality of circuit states corresponds to a different combination of active-device states and parasitic-capacitor states in the circuit.

11. The apparatus of claim 8, wherein each input driver comprises:

a P-type field effect transistor (PFET) coupled between the respective input and a supply rail; and

an N-type field effect transistor (NFET) coupled between the respective input and a ground.

12. A method for powering up a circuit, comprising:

placing the circuit in a circuit state, wherein the circuit state is one of a plurality of circuit states corresponding to a plurality of different capacitances, and the circuit state corresponds to a lowest one of the plurality of capacitances; and

connecting the circuit to a power supply while the circuit is in the circuit state.

13. The method of claim 12, wherein placing the circuit in the circuit state comprises driving a plurality of inputs of the circuit according to a combination of input logic states that places the circuit in the circuit state.

14. The method of claim 13, further comprising, after power up, ceasing driving the plurality of inputs of the circuit according to the combination of input logic states.

15. The method of claim 12, wherein each of the plurality of circuit states corresponds to a different combination of active-device states and parasitic-capacitor states in the circuit.

16. An apparatus for powering up a circuit, comprising:

means for placing the circuit in a circuit state, wherein the circuit state is one of a plurality of circuit states corresponding to a plurality of different capacitances, and the circuit state corresponds to a lowest one of the plurality of capacitances; and

means for connecting the circuit to a power supply while the circuit is in the circuit state.

17. The apparatus of claim 16, wherein the means for placing the circuit in the circuit state comprises means for driving a plurality of inputs of the circuit according to a combination of input logic states that places the circuit in the circuit state.

18. The apparatus of claim 17, further comprising means for ceasing driving the plurality of inputs of the circuit according to the combination of input logic states after power up.

19. The apparatus of claim 16, wherein each of the plurality of circuit states corresponds to a different combination of active-device states and parasitic-capacitor states in the circuit.