INTEGRATED CIRCUIT HAVING AN ENHANCED FUSELESS FUSE STRUCTURE, A METHOD OF MANUFACTURING THE SAME AND A DATA STRUCTURE FOR USE WITH THE FUSELESS FUSE STRUCTURE

• US 20150200020A1
• Filed: 01/13/2014
• Published: 07/16/2015
• Est. Priority Date: 01/13/2014
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Guss, Jesse Max, Hui, Chen, Jothikumar, Sathish
• Granted Patent: US 9,230,678 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/802 by encoding redundancy signals
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

An enhanced fuseless fuse structure is provided herein. Additionally, an IC with an enhanced fuseless fuse structure, a data structure that can be used with this structure and a method of manufacturing an IC are disclosed herein. In one embodiment, the IC includes: (1) a fuse wrapper configured to decode fuseless fuse data for controlling the fuses, (2) JTAG registers configured to store fuse register values in designated blocks, wherein the fuse register values and the designated blocks are determined from the fuseless fuse data and (3) options registers configurable by software to store fuse override data for modifying the fuse register values.

Claims

1. An integrated circuit having fuses for configuring circuitry thereof, said integrated circuit comprising:

a fuse wrapper configured to decode fuseless fuse data for controlling said fuses;

JTAG registers configured to store fuse register values in designated blocks, wherein said fuse register values and said designated blocks are determined from said fuseless fuse data; and

options registers configurable by software to store fuse override data for modifying said fuse register values.

2. The integrated circuit as recited in claim 1 wherein said fuseless fuse data is an instruction for programming said fuse register values onto said JTAG registers, wherein said instruction has a data structure with a data packing efficiency of 50 percent.

3. The integrated circuit as recited in claim 2 wherein said data structure employs a block-based addressing scheme for said JTAG registers.

4. The integrated circuit as recited in claim 2 wherein said data structure includes a data field, a block index field and a chain number field.

5. The integrated circuit as recited in claim 1 further comprising JTAG logic configured to determine said blocks from said fuseless fuse data and load said fuse register values from said fuse data to said determined blocks.

6. The integrated circuit as recited in claim 1 wherein said fuse wrapper includes logic configured to override said fuse register values on said JTAG registers.

7. The integrated circuit as recited in claim 6 wherein said fuse wrapper is configured to override said fuse register values on said JTAG registers with said fuse override data of said options registers.

8. The integrated circuit as recited in claim 1 wherein at least one of said options registers corresponds to a feature of said IC.

9. The integrated circuit as recited in claim 1 wherein said fuse wrapper is further configured to select an option for said feature after fabrication of said integrated circuit and generate fuse output data to set a fuse that corresponds to said option.

10. The integrated circuit as recited in claim 1 further comprising combinational logic coupled to said fuse wrapper and said options registers, said combinational logic configured to generate fuse output data based on inputs from said options registers and from said fuse wrapper, wherein said fuse output data configures said IC.

11. A non-transitory computer readable medium encoded with operating instructions that direct the operations of a processor, said operating instructions having a data structure comprising:

a first field that identifies a single serial register;

a second field that identifies a designated block within said single serial register; and

a third field that includes data to be loaded into said designated block.

12. The non-transitory computer readable medium as recited in claim 11 wherein said single serial register is a JTAG register of an integrated circuit.

13. The non-transitory computer readable medium as recited in claim 11 wherein said data structure has a data packing efficiency of 50 percent.

14. The non-transitory computer readable medium as recited in claim 11 wherein said data structure further includes a fourth field of a single bit that is reserved for additional functionality.

15. The non-transitory computer readable medium as recited in claim 11 wherein said data structure is a 32 bit record structure.

16. The non-transitory computer readable medium as recited in claim 15 wherein said third field has a width of sixteen bits.

17. The non-transitory computer readable medium as recited in claim 16 wherein said second field has a width of ten bits and said first field has a width of five bits.

18. The non-transitory computer readable medium as recited in claim 11 wherein said data is fuseless fuse data for an integrated circuit.

19. The non-transitory computer readable medium as recited in claim 11 wherein said instruction is generated by a fuse wrapper of an integrated circuit.

20. A method of manufacturing an integrated circuit, comprising:

receiving, via a processor, a request for fuseless fuse options for a feature of said integrated circuit;

automatically initiating implementation of a fuseless fuse structure for said requested feature option; and

constructing said fuseless fuse structure.