SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

• US 20150200166A1
• Filed: 01/15/2015
• Published: 07/16/2015
• Est. Priority Date: 01/16/2014
• Status: Abandoned Application

• Current Assignee: AOI Electronics Company Limited
• Original Assignee: Tera Probe Inc. (Powertech Technology Inc)
• Inventors: KONO, Ichiro, NOMURA, Kazufumi, FUKUSHIMA, Masato
• Application Number:
  US14/597,823
• Publication Number:
  US 20150200166A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0384 involving a mechanical process, e.g. planarising the bonding area
• CPC Class Codes: H01L 2224/03903 using different masks
• CPC Class Codes: H01L 2224/0391 Forming a passivation layer after forming the bonding area
• CPC Class Codes: H01L 2224/03914 the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05583 Three-layer coating
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13007 : Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/5252 : comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/5256 : comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/37001 : Yield

Abstract

A manufacturing method of a semiconductor device includes thermally curing a thermosetting resin material layer formed on a semiconductor wafer at a first temperature of 100° C. to 200° C. to form a protective film, preheating the semiconductor wafer having the protective film formed therein at a second temperature and removing water on the surface of the protective film, bias sputtering on the preheated semiconductor wafer, then controlling the temperature of the semiconductor wafer to a third temperature of not more than 200° C., and sputtering a material selected from the group consisting of Ti, TiW, Ta, and a conductive Ti compound to form a first conductive underlayer on the protective film.

Claims

1. A manufacturing method of a semiconductor device, the method comprising the steps of:

preparing a semiconductor wafer comprising memory cells, and a chip region provided with a connection pad electrically connected to the memory cells, a passivation film having an opening being formed on at least part of the connection pad;

forming a thermosetting resin material layer on the wafer, heat treating and curing the thermosetting resin material layer at a first temperature of 100°

C. to 200°

C. or less, and forming a protective film;

preheating the semiconductor wafer having the protective film formed therein at a second temperature, and removing water on the surface of the protective film;

bias sputtering on the preheated semiconductor wafer, and partly removing the surface of the connection pad;

controlling the temperature of the semiconductor wafer which has been subjected to the bias sputtering to a third temperature of 0°

C. to 200°

C.;

sputtering a material selected from the group consisting of titanium, titanium tungsten, tantalum, and a conductive titanium compound to form a first conductive underlayer on the protective film of the semiconductor wafer controlled at the third temperature; and

forming, on at least one part of the first conductive underlayer, one element selected from a redistribution layer, an external connection electrode, a land portion of the external connection electrode, and one under-bump metal.

2. The method according to claim 1, in which the semiconductor wafer comprises a metal wiring fuse trimmed by laser,

in which forming the protective film comprises filling a fuse opening with the protective film, and

which further comprises a step of cutting the semiconductor wafer into pieces after the step of forming one of the redistribution layer, the external connection electrode, the land portion of the external connection electrode, and the under-bump metal.

3. The method according to claim 1, wherein the semiconductor wafer comprises an electrically trimmable fuse circuit, and

the method further comprising electrically trimming the fuse circuit in a step after forming the first conductive underlayer.

4. The method according to claim 3, wherein the electric trimming is performed in a wafer state.

5. The method according to claim 3, further comprising dividing the semiconductor wafer into pieces to obtain semiconductor devices, the electric trimming being performed for each of the divided semiconductor devices.

6. The method according to claim 1, wherein the semiconductor wafer comprises an electrically trimmable fuse circuit, and

electric trimming is performed by the use of the fuse circuit during a wafer test, and the fuse circuit is then further electrically trimmed in a step after the step of forming the first conductive underlayer.

7. The method according to claim 1, wherein the thermosetting resin material is a photosensitive resin, and the formation of the protective film comprises a step of patterning the thermosetting resin material layer in accordance with a photolithographic technique.

8. The method according to claim 1, wherein the protective film is formed by the use of at least one photosensitive resin selected from the group consisting of polyimide resin, polybenzoxazole, and phenol resin material, and the residual stress thereof is 25 Mpa or less.

9. The method according to claim 1, wherein the third temperature is a temperature of not more than 120°

C. or a temperature of not more than the first temperature.

10. The method according to claim 1, wherein the preheating comprises controlling at the second temperature, the bias sputtering comprises controlling at the third temperature, and forming the first conductive underlayer comprises controlling at the third temperature, and

the preheating, the reverse sputtering, and the forming the first conductive underlayer are successively performed under a vacuum.

11. A semiconductor device comprising:

a semiconductor substrate provided with memory cells, a connection pad electrically connected to the memory cells, and a fuse element;

a passivation film formed by providing an opening on at least part of the semiconductor substrate;

a protective film which is buried in at least a fuse opening on the fuse element and which is formed by the use of a resin material that is thermally cured at 100°

C. to 200°

C.; and

one of a redistribution layer including a conductive underlayer made of a material selected from the group consisting of titanium, titanium tungsten, tantalum, and a conductive titanium compound provided on the semiconductor substrate via the protective film, and an external connection electrode.

12. The semiconductor device according to claim 11, wherein the protective film is formed by the use of at least one photosensitive resin selected from the group consisting of polyimide resin, polybenzoxazole, and phenol resin material, and the residual stress thereof is not more than 25 Mpa.

13. The semiconductor device according to claim 11, wherein the thickness of the substrate is 2 μ

m to 100 μ

m.

14. The semiconductor device according to claim 11, wherein the area of the substrate is not less than 40 square millimeters.

15. The semiconductor device according to claim 11, further comprising at least one insulating layer which is provided on at least part of the upper surface, side surface, and rear surface of the semiconductor substrate, and is made of a resin material which is thermally cured at 100°

C. to 200°

C. is.

16. The semiconductor device according to claim 15, wherein the residual stress of the protective film is lower than the residual stress of the insulating layer.

17. The semiconductor device according to claim 15, in which the insulating layer comprises, on the protective film, a redistribution layer protective film formed over at least part of the redistribution layer,

which further comprises an external connection electrode which includes a conductive underlayer made of a material selected from the group consisting of titanium, titanium tungsten, tantalum, and is provided via an opening of the redistribution layer protective film, and

in which the redistribution layer protective film has a residual stress of not more than 25 Mpa, and is formed by the use of at least one photosensitive resin selected from the group consisting of polyimide resin, polybenzoxazole, and phenol resin material.

18. A semiconductor device comprising:

a semiconductor substrate which is provided with memory cells and which comprises a connection pad electrically connected to the memory cells, and an electrically trimmable fuse circuit connected to the memory cells;

a passivation film formed by providing an opening on at least part of the semiconductor substrate;

a protective film which is formed on the passivation film and which is formed by the use of a resin material that is thermally cured at 100°

C. to 200°

C.; and

one of a redistribution layer including a conductive underlayer made of a material selected from the group consisting of titanium, titanium tungsten, tantalum, and a conductive titanium compound provided on the semiconductor substrate via the protective film, and an external connection electrode.

19. The semiconductor device according to claim 18, wherein the protective film is formed by the use of at least one photosensitive resin selected from the group consisting of polyimide resin, polybenzoxazole, and phenol resin material, and the residual stress thereof is not more than 25 Mpa.

20. The semiconductor device according to claim 18, wherein the thickness of the substrate is 2 μ

m to 100 μ

m, the area of the substrate is not more than 40 square millimeters, and the residual stress of the protective film is not more than 25 Mpa.