Capacitively Coupled Input Buffer
First Claim
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1. A buffer circuit comprising:
- a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal;
a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage, the first buffer stage comprising a data hold time; and
,a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse within the data hold time of the first buffer stage such that the second terminal of the capacitor is restored to a level corresponding to a level of the input signal during the data hold time.
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Abstract
A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time.
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Citations
20 Claims
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1. A buffer circuit comprising:
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a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage, the first buffer stage comprising a data hold time; and
,a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse within the data hold time of the first buffer stage such that the second terminal of the capacitor is restored to a level corresponding to a level of the input signal during the data hold time. - View Dependent Claims (2, 3, 4)
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5. A buffer circuit comprising:
a first buffer stage coupled to receive an input signal and a first reference voltage and a second reference voltage, the first buffer stage enabling the input buffer to have independently settable high and low input thresholds based upon the first reference voltage and the second reference voltage. - View Dependent Claims (6)
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7. The buffer circuit of claim 7 wherein:
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the first buffer stage comprises a third transistor and a fourth transistor, a second current handling terminal of the first transistor being coupled to a first current handling terminal of the third transistor; a second current handling terminal of the second transistor being coupled to a first current handling terminal of the fourth transistor; a second current handling terminal of the third transistor and a second current handling terminal of the fourth transistor being coupled together to provide an output of the first buffer stage. - View Dependent Claims (8, 9, 10)
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11. A method comprising:
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receiving an input signal at a first terminal of a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; providing a capacitive input signal to a first buffer stage coupled from a second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage, the first buffer stage comprising a data hold time; generating a control pulse within the data hold time of the first buffer stage; and
,controlling the first buffer stage via the control pulse such that the second terminal of the capacitor is restored to a level corresponding to a level of the input signal during the data hold time. - View Dependent Claims (12, 13, 14)
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15. A method comprising:
receiving an input signal at a first buffer stage; and
, receiving a first reference voltage and a second reference voltage, the first buffer stage enabling the input buffer to have independently settable high and low input thresholds based upon the first reference voltage and the second reference voltage.- View Dependent Claims (16, 17, 18, 19, 20)
Specification