POWER-ON RESET CIRCUIT

• US 20150200653A1
• Filed: 12/15/2014
• Published: 07/16/2015
• Est. Priority Date: 01/16/2014
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Murata Manufacturing Co Limited
• Inventors: Kim, Ryangsu
• Granted Patent: US 9,871,509 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: H03K 17/22 Modifications for ensuring a predetermined initial state when the supply voltage has been applied bi-stable generators H03K3/12
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

A power-on reset circuit includes a first resistor having one end connected to a power source node; a first capacitor connected to another end of the first resistor; a second resistor having one end connected to the power source node; a second capacitor connected to another end of the second resistor; a first inverter having a power source terminal connected to the other end of the first resistor and an input terminal connected to the other end of the second resistor; and a second inverter having a power source terminal connected to the other end of the first resistor, an input terminal connected to an output terminal of the first inverter, and an output terminal electrically connected to a reset signal output terminal.

Claims

1. A power-on reset circuit integrated with a semiconductor chip, the power-on reset circuit comprising:

a first resistor having one end connected to a power source node;

a first capacitor connected to another end of the first resistor;

a second resistor having one end connected to the power source node;

a second capacitor connected to another end of the second resistor;

a first inverter having a power source terminal connected to the other end of the first resistor, an input terminal connected to the other end of the second resistor, and an output terminal; and

a second inverter having a power source terminal connected to the other end of the first resistor, an input terminal connected to the output terminal of the first inverter, and an output terminal electrically connected to a reset signal output terminal.

2. The power-on reset circuit according to claim 1,

wherein a time constant determined by the first resistor and the first capacitor is greater than a time constant determined by the second resistor and the second capacitor.

3. The power-on reset circuit according to claim 1, further comprising:

a third resistor having one end connected to the output terminal of the second inverter and another end connected to the reset signal output terminal; and

a third capacitor connected to the other end of the third resistor.

4. The power-on reset circuit according to claim 1,

wherein each of the first inverter and the second inverter includes a plurality of cascode-connected P-type FETs and an N-type FET connected to the plurality of P-type FETs.

5. The power-on reset circuit according to claim 3, further comprising:

a transistor connected to the third capacitor and discharging the third capacitor,

wherein a control terminal of the transistor is connected to the output terminal of the second inverter.

6. The power-on reset circuit according to claim 2, further comprising:

a third resistor having one end connected to the output terminal of the second inverter and another end connected to the reset signal output terminal; and

a third capacitor connected to the other end of the third resistor.

7. The power-on reset circuit according to claim 2,

wherein each of the first inverter and the second inverter includes a plurality of cascode-connected P-type FETs and an N-type FET connected to the plurality of P-type FETs.

8. The power-on reset circuit according to claim 3,

wherein each of the first inverter and the second inverter includes a plurality of cascode-connected P-type FETs and an N-type FET connected to the plurality of P-type FETs.

9. The power-on reset circuit according to claim 4, further comprising:

a transistor connected to the third capacitor and discharging the third capacitor,

wherein a control terminal of the transistor is connected to the output terminal of the second inverter.