STACKED CONDUCTIVE INTERCONNECT INDUCTOR

• US 20150201495A1
• Filed: 01/14/2014
• Published: 07/16/2015
• Est. Priority Date: 01/14/2014
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: KIM, Daeik Daniel, VELEZ, Mario Francisco, ZUO, Chengjie, YUN, Changhan Hobie, KIM, Jonghae, NOWAK, Matthew Michael
• Application Number:
  US14/155,187
• Publication Number:
  US 20150201495A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/042 Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
• CPC Class Codes: H05K 2201/1003 Non-printed inductor
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor

Abstract

An integrated circuit device includes a first substrate supporting a pair of conductive interconnects, for example pillars. The device also includes a second substrate on the pair of conductive interconnects. The pair of conductive interconnects is arranged to operate as a first 3D solenoid inductor. The device further includes a conductive trace coupling the pair of conductive interconnects to each other.

Claims

1. An integrated circuit device, comprising:

a first substrate supporting a first pair of conductive interconnects;

a second substrate on the first pair of conductive interconnects, the first pair of conductive interconnects arranged to operate as part of a first 3D solenoid inductor; and

a first conductive trace coupling the first pair of conductive interconnects to each other.

2. The integrated circuit device of claim 1, further comprising:

a second pair of conductive interconnects between the first substrate and the second substrate;

a third pair of conductive interconnects supported by the second substrate; and

a third substrate stacked on the second pair of conductive interconnects.

3. The integrated circuit device of claim 2, further comprising:

a second conductive trace coupling the third pair of conductive interconnects to each other, in which the third pair of conductive interconnects is arranged to operate as a second 3D solenoid inductor aligned with the first 3D solenoid inductor.

4. The integrated circuit device of claim 2, further comprising:

a second conductive trace coupling the second pair of conductive interconnects to each other, in which the second pair of conductive interconnects is arranged to operate as a second 3D solenoid inductor.

5. The integrated circuit device of claim 2, further comprising:

a fourth pair of conductive interconnects arranged between the second substrate and the third substrate and coupled to the second pair of conductive interconnects through a plurality of vias;

a second conductive trace coupling one end of the second pair of conductive interconnects to each other and that also goes through the fourth pair of conductive interconnects, the second pair of conductive interconnects and the fourth pair of conductive interconnects arranged to operate as a third 3D solenoid inductor having a height greater than a height of the first 3D solenoid inductor.

6. The integrated circuit device of claim 2, in which the third substrate comprises glass.

7. The integrated circuit device of claim 2, in which a metal-insulator-metal (MIM) capacitor is formed on a surface of the third substrate.

8. The integrated circuit device of claim 1, in which the first pair of conductive interconnects comprise a pair of pillars.

9. The integrated circuit device of claim 1 incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

10. An integrated circuit device, comprising:

a first substrate supporting a first pair of conductive interconnects and a second pair of conductive interconnects;

a second substrate stacked on the first and second pair of conductive interconnects, the second substrate supporting a third pair of conductive interconnects and a fourth pair of conductive interconnects, the second substrate including a pair of vias coupling the second pair of conductive interconnects to the fourth pair of conductive interconnects;

a third substrate stacked on the third and fourth pairs of conductive interconnects;

a first conductive trace coupling the first pair of conductive interconnects to each other to operate as a first stacked 3D solenoid inductor;

a second conductive trace coupling the third pair of conductive interconnects to each other to operate as a second stacked 3D solenoid inductor; and

a third conductive trace coupling one of the second or fourth pair of conductive interconnects to each other to operate as a third stacked 3D solenoid inductor.

11. A back end of line processing method to fabricate an inductive device, comprising:

fabricating a first pair of conductive interconnects on a first substrate;

placing a second substrate on the first pair of conductive interconnects, the first pair of conductive interconnects arranged to operate as a first 3D solenoid inductor; and

fabricating a first conductive trace coupling the first pair of conductive interconnects to each other.

12. The method of claim 11, in which fabricating the first pair of conductive interconnects on the first substrate comprises:

depositing a first conductive layer on the first substrate;

depositing a first photoresist layer on the first conductive layer;

etching the first photoresist layer to pattern the first conductive layer;

stripping the first photoresist layer;

depositing a first interconnect material layer on the patterned first conductive layer;

depositing a second photoresist layer on the deposited first interconnect material layer; and

etching the second photoresist layer to pattern the first interconnect material layer to form the first pair of conductive interconnects.

13. The method of claim 11, further comprising:

fabricating a second pair of conductive interconnects between the first substrate and the second substrate;

fabricating a third pair of conductive interconnects on the second substrate; and

placing a third substrate on the third pair of conductive interconnects.

14. The method of claim 13, further comprising:

fabricating a second conductive trace coupling the third pair of conductive interconnects to each other, in which the third pair of conductive interconnects is arranged to operate as a second 3D solenoid inductor aligned with the first 3D solenoid inductor.

15. The method of claim 13, further comprising:

fabricating a second conductive trace coupling the second pair of conductive interconnects to each other, in which the second pair of conductive interconnects is arranged to operate as a second 3D solenoid inductor.

16. The method of claim 13, further comprising:

fabricating a fourth pair of conductive interconnects between the second substrate and the third substrate;

fabricating a plurality of vias in the second substrate;

coupling the fourth pair of conductive interconnects to the second pair of conductive interconnects through the plurality of vias; and

fabricating a second conductive trace coupling one end of the second pair of conductive interconnects to each other and that also goes through the fourth pair of conductive interconnects, the second pair of conductive interconnects and the fourth pair of conductive interconnects arranged to operate as a third 3D solenoid inductor having a height greater than a height of the first 3D solenoid inductor.

17. The method of claim 11, further comprising incorporating the inductive device into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

18. An integrated circuit device, comprising:

a first substrate supporting a first pair of means for interconnecting;

a second substrate on the first pair of interconnecting means, the first pair of interconnecting means arranged to operate as a first 3D solenoid inductor; and

a first conductive means coupling the first pair of interconnecting means to each other.

19. The integrated circuit device of claim 18, further comprising:

a second pair of means for interconnecting between the first substrate and the second substrate;

a third pair of means for interconnecting supported by the second substrate; and

a third substrate stacked on the second pair of interconnecting means.

20. The integrated circuit device of claim 19, further comprising:

a second conductive means coupling the third pair of interconnecting means to each other, in which the third pair of interconnecting means is arranged to operate as a second 3D solenoid inductor aligned with the first 3D solenoid inductor.

21. The integrated circuit device of claim 19, further comprising:

a second conductive means coupling the second pair of interconnecting means to each other, in which the second pair of interconnecting means is arranged to operate as a second 3D solenoid inductor.

22. The integrated circuit device of claim 19, further comprising:

a fourth pair of means for interconnecting arranged between the second substrate and the third substrate and coupled to the second pair of interconnecting means through a plurality of vias; and

a second conductive means coupling one end of the second pair of interconnecting means to each other and that also goes through the fourth pair of interconnecting means, the second pair of interconnecting means and the fourth pair of interconnecting means arranged to operate as a third 3D solenoid inductor having a height greater than a height of the first 3D solenoid inductor.

23. The integrated circuit device of claim 19, in which the third substrate comprises glass.

24. The integrated circuit device of claim 19, in which a metal-insulator-metal (MIM) capacitor is formed on a surface of the third substrate.

25. The integrated circuit device of claim 18, in which the first pair of interconnecting means comprise a pair of pillars.

26. The integrated circuit device of claim 18 incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.