DESIGN AUTOMATION FOR MONOLITHIC 3D DEVICES
First Claim
Patent Images
1. A method of designing a 3D Integrated Circuit, the method comprising:
- performing partitioning to at least a first strata and a second strata;
thenperforming a first placement of said first strata using a 2D placer executed by a computer,wherein said 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and
performing a second placement of said second strata based on said first placement,wherein said partitioning comprises a partition between logic and memory, andwherein said logic comprises at least one decoder representation for said memory.
1 Assignment
0 Petitions
Accused Products
Abstract
A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a first strata and a second strata; then performing a first placement of the first strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of the second strata based on the first placement, where the partitioning includes a partition between logic and memory, and where the logic includes at least one decoder representation for the memory.
21 Citations
20 Claims
-
1. A method of designing a 3D Integrated Circuit, the method comprising:
-
performing partitioning to at least a first strata and a second strata;
thenperforming a first placement of said first strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of said second strata based on said first placement, wherein said partitioning comprises a partition between logic and memory, and wherein said logic comprises at least one decoder representation for said memory. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A method of designing a 3D Integrated Circuit, the method comprising:
-
performing partitioning to at least a first strata and a second strata;
thenperforming a first placement of said first strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of said second strata based on said first placement, wherein said partitioning comprises a partition between logic and memory, and wherein said logic comprises at least one decoder for said memory. - View Dependent Claims (8, 9, 10, 11, 12, 13)
-
-
14. A method of designing a 3D Integrated Circuit, the method comprising:
-
performing partitioning to at least a first strata and a second strata;
thenperforming a first placement of said first strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of said second strata based on said first placement, wherein said partitioning comprises splitting a plurality of cells into a high performance group to said first strata and a low performance group to said second strata. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification