THREE-DIMENSIONAL WORDLINE SHARING MEMORY

• US 20150206555A1
• Filed: 01/21/2014
• Published: 07/23/2015
• Est. Priority Date: 01/21/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YANG, Hao-I, CHEN, Yi-Tzu, CHANG, Cheng-Jen, LIN, Geng-Cing, HU, Yu-Hao
• Granted Patent: US 9,299,391 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.

Claims

1. A three dimensional (3D) circuit, comprising:

a first layer including at least a first memory cell;

a second layer including at least a second memory cell, the second layer disposed in a vertical stack with the first layer; and

a wordline shared by the first memory cell and the second memory cell.

2. The 3D circuit of claim 1, wherein the first memory cell and the second memory cell are horizontally adjacent memory cells coupled to different bit lines.

3. The 3D circuit of claim 1, wherein the first memory cell and the second memory cell are vertically adjacent memory cells coupled to different bit lines.

4. The 3D circuit of claim 3, wherein the different bit lines include a first bit line in the first layer and a second bit line in the second layer.

5. The 3D circuit of claim 1, wherein the first layer includes a first plurality of memory cells, the second layer includes a second plurality of memory cells, and the wordline is shared by the first plurality of memory cells and the second plurality of memory cells.

6. The 3D circuit of claim 5, wherein the wordline extends horizontally across one of the first layer or the second layer and is shared with the first plurality of memory cells disposed vertically above the wordline and with the second plurality of memory cells disposed vertically below the wordline.

7. The 3D circuit of claim 5, wherein the wordline extends horizontally across one of the first layer or the second layer and is shared with the first plurality of memory cells and the second plurality of memory cells both disposed vertically below the wordline.

8. The 3D circuit of claim 1, further comprising a first plurality of memory cells disposed in the first layer, a second plurality of memory cells disposed in the second layer, and respective pluralities of memory cells disposed in adjacent respective layers below the first and second layers, wherein the wordline extends horizontally across and above the first plurality of memory cells and is shared with the first plurality of memory cells, the second plurality of memory cells, and the respective pluralities of memory cells all disposed vertically below the wordline.

9. The 3D circuit of claim 1, further comprising a first plurality of memory cells disposed above the first layer in respective layers above the first layer, and a second plurality of memory cells disposed below the second layer in respective layers below the second layer, wherein the wordline is a horizontal wordline disposed between the first layer and the second layer and the horizontal wordline is shared with the first plurality of memory cells and the second plurality of memory cells.

10. The 3D circuit of claim 1, wherein the first memory cell and the second memory cells are adjacent static random access memory cells.

11. The 3D circuit of claim 1, wherein the wordline extends vertically from the first layer to the second layer and is shared among memory cells on separate layers with memory cells including the first memory cell disposed horizontally to the left of the wordline and memory cells including the second memory cell disposed horizontally to the right of the wordline.

12. A semiconductor memory, comprising:

a bit cell array, comprising;

a first memory cell of the bit cell array disposed in a first layer;

a second memory cell of the bit cell array disposed in a second layer, the second layer disposed in a vertical stack with the first layer; and

a wordline shared by the first memory cell and the second memory cell of the bit cell array.

13. The semiconductor memory of claim 12, wherein the first memory cell and the second memory cell are vertically adjacent memory cells coupled to different bit lines.

14. The semiconductor memory of claim 13, wherein the different bit lines include a first bit line in the first layer and a second bit line in the second layer.

15. A method, comprising:

forming circuitry on a first layer, the circuitry on the first layer including a first memory cell;

forming circuitry on a second layer, the circuitry on the second layer including a second memory cell; and

forming a wordline such that the wordline is shared by the first memory cell and the second memory cell.

16. The method of claim 15, wherein the first memory cell and the second memory cells are formed as horizontally adjacent memory cells coupled to different bit lines.

17. The method of claim 16, wherein the first memory cell and the second memory cell are formed as vertically adjacent memory cells coupled to different bit lines.

18. The method of claim 15, wherein the method further comprises coupling the first layer and the second layer together.

19. The method of claim 15, wherein the method comprises coupling the first memory cell and the second memory cell via the wordline using through-silicon-vias.

20. The method of claim 15, wherein the first layer includes a first plurality of memory cells for the word, the second layer includes a second plurality of memory cells for the word, and the wordline for the word is shared by the first plurality of memory cells and the second plurality of memory cells.