SEMICONDUCTOR PACKAGE

• US 20150206855A1
• Filed: 07/03/2014
• Published: 07/23/2015
• Est. Priority Date: 01/22/2014
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: LIN, Tzu-Hung
• Application Number:
  US14/323,107
• Publication Number:
  US 20150206855A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

The invention provides a semiconductor package. The semiconductor package includes a first semiconductor die having pads thereon. A first via and a second via are respectively disposed on the first semiconductor die. The first via connects to at least two of the pads of the first semiconductor die.

Claims

1. A semiconductor package, comprising:

a first semiconductor die having pads thereon; and

a first via and a second via respectively disposed on the first semiconductor die, wherein the first via connects to at least two of the pads of the first semiconductor die.

2. The semiconductor package as claimed in claim 1, wherein the second via connects to a single one of the pads of the first semiconductor die.

3. The semiconductor package as claimed in claim 1, wherein the first via is mesh-shaped or ring-shaped from a plan view.

4. The semiconductor device as claimed in claim 1, wherein an area of the first via is larger than that of the second via.

5. The semiconductor package as claimed in claim 1, wherein the at least two of the pads are power pads or ground pads.

6. The semiconductor device as claimed in claim 1, wherein an area of the first via is larger than that of any of the pads.

7. The semiconductor device as claimed in claim 1, further comprising:

a redistribution layer (RDL) structure having a first conductive trace and a second conductive trace thereon, wherein the first via and the second via are in contact with the first conductive trace and the second conductive trace, respectively.

8. The semiconductor device as claimed in claim 7, further comprising:

a molding substrate surrounding first semiconductor die, being in contact with the redistribution layer (RDL) structure and the first semiconductor die; and

a first package mount and a second package mount disposed on a surface of the redistribution layer (RDL) structure away from the first semiconductor die wherein the first package mount and the second package mount are coupled to the first conductive trace and the second conductive trace, respectively.

9. The semiconductor package as claimed in claim 1, further comprising:

a second semiconductor die disposed beside the first semiconductor die or on the first semiconductor die.

10. A semiconductor package, comprising:

a first semiconductor die having a first pad and a second pad thereon, wherein the first and second pads are both power pads or ground pads; and

a first via disposed on the first semiconductor die, wherein the first via connects to both the first and second pads of the first semiconductor die.

11. The semiconductor device as claimed in claim 10, further comprising:

a second via disposed on the first semiconductor die, wherein the second via connects to a third pad of the first semiconductor die only.

12. The semiconductor package as claimed in claim 10, wherein the first via is mesh-shaped or ring-shaped from a plan view.

13. The semiconductor device as claimed in claim 11, wherein an area of the first via is larger than that of any of the first and second pads.

14. The semiconductor device as claimed in claim 11, wherein an area of the first via is larger than that of the second via.

15. The semiconductor device as claimed in claim 11, further comprising:

a redistribution layer (RDL) structure having a first conductive trace and a second conductive trace thereon, wherein the first via and the second via are in contace with the first conductive trace and the second conductive trace, respectively.

16. The semiconductor device as claimed in claim 15, further comprising:

a molding substrate surrounding first semiconductor die, being in contact with the redistribution layer (RDL) structure and the first semiconductor die; and

a first package mount and a second package mount disposed on a surface of the redistribution layer (RDL) structure away from the first semiconductor die wherein the first package mount and the second package mount are coupled to the first conductive trace and the second conductive trace, respectively.

17. The semiconductor package as claimed in claim 10, further comprising:

a second semiconductor die disposed beside the first semiconductor die or on the first semiconductor die.

18. A semiconductor package, comprising:

a first semiconductor die having pads thereon; and

a first via disposed on the first semiconductor die, wherein the first conductive bump connects to the pads of the first semiconductor die, wherein the first via is mesh-shaped or ring-shaped from a plan view.

19. The semiconductor device as claimed in claim 18, further comprising:

a second via disposed on the first semiconductor die, wherein the second via connects to an additional single pad of the first semiconductor die.

20. The semiconductor package as claimed in claim 19, wherein the pads are power pads or ground pads.

21. The semiconductor device as claimed in claim 19, wherein an area of the first via is larger than that of any of the pads.

22. The semiconductor device as claimed in claim 19, wherein an area of the first via is larger than that of the second via.

23. The semiconductor device as claimed in claim 22, further comprising:

a redistribution layer (RDL) structure having a first conductive trace and a second conductive trace thereon, wherein the first via and the second via are in contact with the first conductive trace and the second conductive trace, respectively.

24. The semiconductor device as claimed in claim 23, comprising:

a molding substrate surrounding first semiconductor die, being in contact with the redistribution layer (RDL) structure and the first semiconductor die; and

a first package mount and a second package mount disposed on a surface of the redistribution layer (RDL) structure away from the first semiconductor die wherein the first package mount and the second package mount are coupled to the first conductive trace and the second conductive trace, respectively.

25. The semiconductor package as claimed in claim 18, further comprising:

a second semiconductor die disposed beside the first semiconductor die or on the first semiconductor die.