Semiconductor Package and Methods of Forming Same

• US 20150206866A1
• Filed: 04/14/2014
• Published: 07/23/2015
• Est. Priority Date: 01/17/2014
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Yee, Kuo-Chung, Lii, Mirng-Ji, Lee, Chien-Hsun, Wu, Jiun Yi
• Application Number:
  US14/252,261
• Publication Number:
  US 20150206866A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/37001 : Yield

Abstract

An embodiment package-on-package (PoP) device includes a fan-out structure, one or more memory chips, and a plurality of connectors bonding the one or more memory chips to the fan-out structure. The fan-out structure includes a logic chip, a molding compound encircling the logic chip, and a plurality of conductive pillars extending through the molding compound.

Claims

1. A package-on-package (PoP) device comprising:

a first fan-out structure comprising;

a logic chip;

a first molding compound encircling the logic chip; and

a first plurality of conductive pillars extending through the first molding compound;

a second fan-out structure comprising;

one or more memory chips;

a second molding compound encircling the one or more memory chips; and

a second plurality of conductive pillars extending through the second molding compound; and

a first plurality of connectors bonding the first fan-out structure to the second fan-out structure.

2. The PoP device of claim 1, wherein the first fan out structure further comprises one or more redistribution layers (RDLs) electrically connecting the second fan-out structure to the logic chip and the first plurality of conductive pillars.

3. The PoP device of claim 1, further comprising a package structure bonded to a surface of the first fan-out structure opposing the second fan-out structure.

4. The PoP device of claim 3, wherein the package structure comprises:

a plurality of stacked dynamic random access memory (DRAM) chips;

a package substrate electrically connected to the plurality of stacked DRAM chips; and

a second plurality of connectors electrically connecting the package substrate to the first fan-out structure, wherein the second plurality of connectors is aligned with the first plurality of conductive pillars.

5. The PoP device of claim 1, wherein lateral surfaces of the logic chip, the first molding compound, and the first plurality of conductive pillars are substantially level, and wherein lateral surfaces of the one or more memory chips, the second molding compound, and the second plurality of conductive pillars are substantially level.

6. The PoP device of claim 1, further comprising a plurality of ball grid array (BGA) balls electrically connected to the second plurality of conductive pillars, wherein the plurality of BGA balls are disposed on a surface of the second fan-out structure opposing the first fan-out structure.

7. The PoP device of claim 1, wherein the logic chip is an application processor, and wherein the one or more memory chips include one or more wide input/output (IO) chips.

8. The PoP device of claim 1, wherein the first and the second pluralities of conductive pillars comprise copper, silver, gold, or a combination thereof.

9. A package-on-package (PoP) device comprising:

a fan-out structure comprising;

a logic chip;

a molding compound encircling the logic chip; and

a plurality of through molding vias (TMVs) extending through the molding compound;

one or more memory chips bonded to a first surface of the fan-out structure; and

a first package substrate bonded to the first surface of the fan-out structure, wherein the first package substrate comprises a through hole, and wherein the one or more memory chips are disposed in the through hole.

10. The PoP device of claim 9, wherein the fan-out structure further comprises one or more redistribution layers (RDLs) on the logic chip and the molding compound, wherein the one or more RDLs electrically connect the one or more memory chips and the package substrate to the logic chip and the plurality of TMVs.

11. The PoP device of claim 9, further comprising a package structure bonded to a second surface of the fan-out structure opposing the first surface of the fan-out structure, wherein the package structure is a low-power double data rate 2 (LP-DDR2) package or a LP-DDR3 package.

12. The PoP device of claim 9, wherein the logic chip is an application processor, and wherein the one or more memory chips include one or more wide input/output (IO) chips.

13. The PoP device of claim 9, further comprising a plurality of ball grid array (BGA) balls disposed on a surface of the first package substrate opposite the fan-out structure, wherein interconnect structures in the first package substrate electrically connect the plurality of BGA balls to the fan-out structure.

14. The PoP device of claim 9, wherein the first package substrate is an organic substrate or a ceramic substrate.

15. The PoP device of claim 9, wherein the plurality of TMVs comprise copper, silver, gold, or a combination thereof.

16. A method for forming a package-on-package (PoP) device comprising:

forming a first fan-out structure, wherein forming the first fan-out structure comprises;

patterning a first plurality of openings in a photoresist layer over a carrier;

filling the first plurality of openings with a conductive material to form a plurality of conductive pillars;

removing the photoresist layer leaving a second plurality of openings between each of the plurality of conductive pillars;

disposing a logic chip over the carrier in one of the second plurality of openings; and

filling the second plurality of openings with a molding compound, wherein lateral surfaces of the molding compound and the logic chip are substantially level; and

bonding one or more wide input/output (IO) chips to the first fan out structure, wherein the one or more wide IO chips is electrically connected to the logic chip.

17. The method of claim 16, wherein forming the first fan-out structure further comprises forming one or more redistribution layers (RDLs) on the logic chip, the molding compound, and the plurality of conductive pillars.

18. The method of claim 16 further comprising after bonding the one or more wide IO chips, bonding a package structure to a surface of the first fan-out structure opposing the one or more wide IO chips, wherein the package structure comprises:

a plurality of stacked dynamic random access memory (DRAM) chips;

a first package substrate electrically connected to the plurality of stacked DRAM chips; and

a plurality of connectors electrically connecting the first package substrate to the first fan-out structure, wherein the plurality of connectors is aligned with the plurality of conductive pillars.

19. The method of claim 16 further comprising bonding a second package substrate to the first fan-out structure, wherein the second package substrate comprises a through hole, and wherein bonding the one or more wide IO chips comprises disposing the one or more wide IO chips in the through hole.

20. The method of claim 16, wherein bonding the one or more wide IO chips comprises bonding a second fan-out structure comprising the one or more wide IO chips to the first fan-out structure.