DATA PROCESSING DEVICE AND DRIVING METHOD THEREOF

• US 20150207509A1
• Filed: 01/15/2015
• Published: 07/23/2015
• Est. Priority Date: 01/17/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Granted Patent: US 9,379,713 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H03K 19/018507 Interface arrangements
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories

Abstract

In a processor or the like including a reconfigurable (RC) circuit, the RC circuit is used to form a test circuit to test a core, a cache memory, or the like, and then part of the RC circuit is used as an auxiliary cache memory. When a memory can store data after stop of power supply, a startup routine program (SRP) of the processor can be stored therein. For example, after the test, an SRP is loaded to a memory in the RC circuit from an external ROM or the like, and when power is resupplied to the processor, a startup operation is performed using the loaded SRP. When the processor is in a normal operation state, this memory is used as an auxiliary cache memory and the SRP is overwritten. The SRP is loaded to the memory again at the end of use of the processor.

Claims

1. A semiconductor device comprising:

a reconfigurable circuit comprising a first wiring group, a second wiring group, a switch array matrix, and a logic circuit, the logic circuit comprising a switch,

wherein the switch array matrix comprises a plurality of programmable switches,

wherein signals are configured to be input to the logic circuit via a plurality of wirings of the second wiring group,

wherein an output of the logic circuit is configured to be input to the first wiring group via the switch, and

wherein each of the plurality of programmable switches is configured to make an electrical connection and an electrical disconnection between one wiring of the first wiring group and one wiring of the second wiring group.

2. The semiconductor device according to claim 1,

wherein the reconfigurable circuit is configured to function as a test circuit when a test for a chip is performed, function as a nonvolatile memory storing a startup routine program when a processor starts up, and function as a memory in a normal operation.

3. The semiconductor device according to claim 2, wherein the memory is a cache memory of the processor.

4. The semiconductor device according to claim 1, wherein the switch is a tri-state buffer.

5. The semiconductor device according to claim 1, further comprising a third wiring group designed to be parallel to the first wiring group, a fourth wiring group and a fifth wiring group, both designed to be parallel to the second wiring group,

wherein each of the plurality of programmable switches comprises a first switching element, a second switching element, and a capacitor,

wherein the first switching element is configured to be on or off according to electrical charges stored in the capacitor,

wherein the second switching element is configured to be on or off according to a signal of one wiring of the fifth wiring group,

wherein each of the plurality of programmable switches is configured to make the electrical connection between the one wiring of the first wiring group and the one wiring of the second wiring group when both the first switching element and the second switching element are on,

wherein data corresponding to signals transmitted by one wiring of the third wiring group is configured to be input to each of the plurality of programmable switches as the electrical charges, and

wherein inputting the data to each of the plurality of programmable switches is configured to be controlled by signals of one wiring of the fourth wiring group.

6. The semiconductor device according to claim 5, further comprising a transistor in each of the plurality of programmable switches,

wherein an operation of the transistor is configured to be controlled by the signals of the one wiring of the fourth wiring group, and

wherein the transistor comprises a channel formation region comprising an oxide semiconductor.

13. A method for driving the semiconductor device according to claim 2, comprising:

reconfiguring the reconfigurable circuit as the test circuit;

performing the test by using the test circuit; and

reconfiguring the reconfigurable circuit as the memory after the test.

7. A semiconductor device comprising:

a reconfigurable circuit comprising a first wiring group, a second wiring group, a first switch array matrix, a second switch array matrix, a third switch array matrix, and a logic circuit, the logic circuit comprising a first switch, a second switch, and a third switch,

wherein each of the first switch array matrix, the second switch array matrix, and the third switch array matrix comprises a plurality of programmable switches,

wherein each of the plurality of programmable switches is configured to make an electrical connection and an electrical disconnection between one wiring of the first wiring group and one wiring of the second wiring group,

wherein signals are configured to be input to the logic circuit via a plurality of wirings of the second wiring group,

wherein a first output of the logic circuit is configured to be input to a first group of the first wiring group via the first switch,

wherein a second output of the logic circuit is configured to be input to a second group of the first wiring group via the second switch,

wherein a third output of the logic circuit is configured to be input to a third group of the first wiring group via the third switch, and

wherein the first group of the first wiring group passes through the first switch array matrix, the second group of the first wiring group passes through the second switch array matrix, and the third group of the first wiring group passes through the third switch array matrix.

8. The semiconductor device according to claim 7,

wherein the reconfigurable circuit is configured to function as a test circuit when a test for a chip is performed, function as a nonvolatile memory storing a startup routine program when a processor starts up, and function as a memory in a normal operation.

9. The semiconductor device according to claim 8, wherein the memory is a cache memory of the processor.

10. The semiconductor device according to claim 7, wherein each of the first switch, the second switch, and the third switch is a tri-state buffer.

11. The semiconductor device according to claim 7, further comprising a third wiring group designed to be parallel to the first wiring group, a fourth wiring group and a fifth wiring group, both designed to be parallel to the second wiring group,

wherein each of the plurality of programmable switches comprises a first switching element, a second switching element, and a capacitor,

wherein the first switching element is configured to be on or off according to electrical charges stored in the capacitor,

wherein the second switching element is configured to be on or off according to a signal of one wiring of the fifth wiring group,

wherein each of the plurality of programmable switches is configured to make the electrical connection between the one wiring of the first wiring group and the one wiring of the second wiring group when both the first switching element and the second switching element are on,

wherein data corresponding to signals transmitted by one wiring of the third wiring group is configured to be input to each of the plurality of programmable switches as the electrical charges, and

wherein inputting the data to each of the plurality of programmable switches is configured to be controlled by signals of one wiring of the fourth wiring group.

12. The semiconductor device according to claim 11, further comprising a transistor in each of the plurality of programmable switches,

wherein an operation of the transistor is configured to be controlled by the signals of the one wiring of the fourth wiring group, and

wherein the transistor comprises a channel formation region comprising an oxide semiconductor.

14. A method for driving the semiconductor device according to claim 8, comprising:

reconfiguring the reconfigurable circuit as the test circuit;

performing the test by using the test circuit; and

reconfiguring the reconfigurable circuit as the memory after the test.

15. A method for driving a semiconductor device comprising a reconfigurable circuit comprising a logic circuit, comprising:

supplying power to the reconfigurable circuit;

loading a startup routine program into a processor from the reconfigurable circuit if the startup routine program is stored in the reconfigurable circuit;

loading the startup routine program into the reconfigurable circuit from a ROM if the startup routine program is not stored in the reconfigurable circuit;

starting up the processor by using the startup routine program; and

reconfiguring the reconfigurable circuit as a memory.

16. The method for driving the semiconductor device, according to claim 15, wherein the memory is a cache memory.

17. The method for driving the semiconductor device, according to claim 16, wherein the cache memory is used as a tag memory.

18. The method for driving the semiconductor device, according to claim 15, further comprising:

reconfiguring the reconfigurable circuit as a test circuit; and

performing a test for a chip by using the test circuit before reconfiguring the reconfigurable circuit as the memory.

19. The method for driving the semiconductor device, according to claim 18,

wherein the chip comprises the processor, and

wherein the processor comprises the reconfigurable circuit.