ERROR DETECTION AND REJECTION FOR A DIAGNOSTIC TESTING SYSTEM

• US 20150212872A1
• Filed: 04/10/2015
• Published: 07/30/2015
• Est. Priority Date: 04/12/2007
• Status: Active Grant

• Current Assignee: Trividia Health, Inc. (Sinocare, Inc.)
• Original Assignee: Nipro Diagnostics, Inc.
• Inventors: Modzelewski, Brent E., Kayihan, Ferhan, Cardello, Edward
• Granted Patent: US 10,013,297 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01N 2035/00851 process control parameters
• CPC Class Codes: G01N 33/48771 Coding of information, e.g. calibration data, lot number
• CPC Class Codes: G01N 35/00732 Identification of carriers, materials or components in automatic analysers
• CPC Class Codes: G06F 11/0763 by bit configuration check, e.g. of formats or tags
• CPC Class Codes: Y10T 436/11 Automated chemical analysis

Abstract

A system for measuring a property of a sample is provided. The system comprises a diagnostic measuring device having a memory and a diagnostic test strip for collecting the sample. The strip has embedded thereon a pattern representative of at least first data and second data, the first data being data representing at least one of parameters related to measuring the property, codes usable for calibration of the diagnostic measuring device, or parameters indicating proper connection between the measuring device and the test strip and the second data usable for detecting and rejecting potential errors affecting the proper measurement of the property.

Claims

1. A method for minimizing the impact of potential errors that may occur when a device reads a diagnostic test strip including a first code comprising a plurality of bits arranged in a physical arrangement, the method comprising:

determining a probability of each bit to cause a read error; and

constructing a logical arrangement of the bits different than the physical arrangement based on the probability, wherein the logical arrangement corn rises the bits arranged such that the impact of potential read errors is minimized.

2. The method according to claim 1, wherein the logical arrangement comprises the bits arranged such that the bit having the highest probability of causing a read error is logically replaced by the bit having the lowest probability of causing a read error, and the bit having the lowest probability of causing a read error is logically replaced by the bit having the highest probability of causing a read error.

3. The method according to claim 2, wherein the logical arrangement results in a second code which is read in sequence.

4. The method according to claim 2, wherein the logical arrangement results in a second code which is not read in sequence.

5. The method according to claim 1 further comprising performing an error detection and rejection algorithm on the logically arranged code and determining the constituent level of the fluid if the error detection and rejection algorithm detects an acceptable error or does not detect an error in the logically arranged code.

6. A system for measuring a property of a sample, comprising:

a diagnostic test strip for collecting the sample, the strip having information embedded thereon;

a diagnostic measuring device for receiving the test strip, reading the embedded information, and measuring the sample; and

the diagnostic device further comprising an error detection routine for detecting errors in the embedded information, the error detection routing comprising;

determining a probability of each bit to cause a read error;

constructing a logical arrangement of the bits different than the physical arrangement based on the probability, wherein the logical arrangement corn rises the bits arranged such that the impact of potential read errors is minimized;

performing an error detection and rejection algorithm on the logically arranged code; and

determining the constituent level of the fluid if the error detection and rejection algorithm detects an acceptable error or does not detect an error in the logically arranged code.

7. The system according to claim 6, wherein the logical arrangement comprises the bits arranged such that the bit having the highest probability of causing a read error is logically replaced by the bit having the lowest probability of causing a read error, and the bit having the lowest probability of causing a read error is logically replaced by the bit having the highest probability of causing a read error.

8. The system according to claim 7, wherein the logical arrangement results in a second code which is read in sequence.

9. The system according to claim 7, wherein the logical arrangement results in a second code which is not read in sequence.