METHOD FOR RELIABLY ADDRESSING A LARGE FLASH MEMORY AND FLASH MEMORY

• US 20150212935A1
• Filed: 06/16/2014
• Published: 07/30/2015
• Est. Priority Date: 01/24/2014
• Status: Active Grant

• Current Assignee: Hyperstone GmbH (Swissbit AG)
• Original Assignee: Hyperstone GmbH (Swissbit AG)
• Inventors: ROEDER, MARTIN, SEIDEL, THOMAS
• Granted Patent: US 9,311,234 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A flash memory for a host system has a multiplicity of memory blocks. The memory blocks are subdivided into memory pages which can be written to and each memory page are also subdivided into partial pages and each partial page having a physical partial page address which is assigned a logical partial page address which can be addressed. The physical partial page addresses assigned to the logical partial page addresses are able to be determined using hierarchically organized structures of address tables for converting logical partial page addresses into physical partial page addresses. The multiplicity of memory blocks of the flash memory are divided into areas which comprise at least one static area of memory blocks which have been written to, a write area to which new and changed useful data are written, a block management area which stores management data for the memory blocks, and a logbook area.

Claims

1. A flash memory for a host system, comprising:

a controller;

a volatile cache memory connected to said controller; and

a multiplicity of memory blocks which can be erased in a respective erase process and connected to said controller, said memory blocks being subdivided into memory pages which can be written to in a respective write process and each memory page also being subdivided into partial pages and each partial page having a physical partial page address which can be assigned logical sector addresses which can be addressed by the host system, physical partial page addresses assigned to the logical sector addresses being able to be determined using hierarchically organized structures of address tables for converting the logical sector addresses into the physical partial page addresses, the address tables having a size of a partial memory page, said multiplicity of memory blocks divided into areas which contain at least one static area of memory blocks which have been written to, a write area to which new and changed useful data are written, a block management area which stores management data for said memory blocks, and a logbook area, and the physical partial page addresses of said static area and of said write area can be determined from the logical sector addresses using a useful data address table structure, the physical partial page addresses of said block management area can be determined using a block management address table structure, and changes to the address tables can be recorded in said volatile cache memory and in partial memory pages of said logbook area.

2. The flash memory according to claim 1, wherein said multiplicity of memory blocks have a commit area partitioned off, said commit area contains at least pointers to the useful data address table structure, to the block management address table structure, to a start of the write area, to a start of the logbook, to a start of the block management area and to a current end of the block management area.

3. The flash memory according to claim 1, wherein said memory blocks are subdivided into interleave units, said memory blocks of said interleave units can be used simultaneously.

4. A method for managing a multiplicity of memory pages in a flash memory of a host system, which comprises the steps of:

performing the following steps in an event of a write instruction from the host system for useful data at a logical sector address;

searching for a new free memory page in a memory block of a write area; and

updating a useful data address table structure with respect to a new assignment of the logical sector address to a physical partial page address, management data relating to memory blocks belonging to a physical partial page addresses are updated, and a changed address assignment is noted in a cache memory.

5. The method according to claim 4, which further comprises managing properties of the memory blocks in partial memory pages of a block management area and the partial memory pages are addressed using a block management address table structure which is constructed like a useful data address table structure.

6. The method according to claim 5, wherein address table structures contain a lowermost level of the partial memory pages which respectively stores a number Np of the physical partial page addresses or a number Nc of block counters which fills a partial memory page, and levels above each contain a number of partial memory pages each storing as many partial page pointers to the partial memory pages of the level below as are held by a partial memory page, and an uppermost level of the address table structures is respectively formed by an input partial memory page storing a number of pointers which corresponds to a number of the partial memory pages in a next level.

7. The method according to claim 6, wherein pointers to input partial memory pages of the address table structures are held in a commit area.

8. The method according to claim 6, wherein the physical partial page address for the logical sector address in the address table structure is determined by means of the following steps:

determining a value x of the logical sector address; and

recursively determining the physical partial page address in respective next higher levels of associated address table structure using an entry i with relationships i=x mod Np and y=└

x/Np┘

.

9. The method according to claim 7, which further comprises:

storing the management data relating to the memory blocks in block counters for each memory block and the block counters are constructed as tuples with a fixed width containing details of an erase counter, a read counter, a validity counter for each memory block and status flags.

10. The method according to claim 5, wherein an entry in levels k>

0 of the block management address table structure contains details of the physical partial page address of a partial page in a next lower level, a minimum use classes of obsolete and valid memory blocks and a maximum validity counter of all associated block counters.

11. The method according to claim 4, which further comprises providing a separate useful data address table structure, a separate block management address table structure, a separate logbook, a separate static area and a separate write area for each interleave unit.