INTEGRAL FABRICATION OF ASYMMETRIC CMOS TRANSISTORS FOR AUTONOMOUS WIRELESS STATE RADIOS AND SENSOR/ACTUATOR NODES

• US 20150213180A1
• Filed: 01/30/2014
• Published: 07/30/2015
• Est. Priority Date: 01/30/2014
• Status: Active Grant

• Current Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Original Assignee: Cambridge Silicon Radio Limited (Qualcomm, Inc.)
• Inventors: Herberholz, Rainer
• Granted Patent: US 9,336,346 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 23/00 Details of semiconductor or other solid state devices H01L25/00 takes precedence ; structural arrangements for testing or measuring during manufacture or treatment, or for reliability measurements H01L22/00; arrangements for connecting or disconnecting semiconductor or solid-state bodies, or methods related thereto H01L24/00; finger print sensors G06V40/12
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of arranging asymmetrically doped CMOS transistors in a semiconductor wafer that forms base cells within a plurality of logic standard cells in a CMOS process technology that includes conventional symmetric CMOS transistors having different threshold voltages. The asymmetrically doped CMOS transistors have a gate length exceeding 1.5 times the minimum gate length of the symmetric CMOS transistors. Regions defined by electrical junctions directly adjacent to the gate of the asymmetric transistors are formed by an implant mask exposing an area of the wafer on the source side of the transistor to receive the junction implant of the symmetric CMOS transistors with a higher threshold voltage while shielding the drain area, and a further implant mask exposing an area of the wafer on the drain side of the transistor to receive the junction implant of the symmetric CMOS transistors with a lower threshold voltage while shielding the source area.

Claims

1. A method of arranging asymmetrically doped CMOS transistors in a semiconductor wafer, said method of arrangement forming base cells within a plurality of logic standard cells in a CMOS process technology comprising conventional, symmetric CMOS transistors having different threshold voltages distinguished by junction implants forming the electrical junctions directly adjacent to the gate;

said asymmetrically doped CMOS transistors having a gate length exceeding 1.5 times the minimum gate length of the symmetric CMOS transistors, whereby the regions defined by the electrical junctions directly adjacent to the gate of the asymmetric transistors are formed by;

an implant mask from a plurality of implant masks that exposes an area of the wafer on the source side of the transistor to receive the junction implant of the symmetric CMOS transistors with higher threshold voltage while shielding the drain area, and

a further implant mask from said plurality of implant masks that exposes an area of the wafer on the drain side of the transistor to receive the junction implant of the symmetric CMOS transistors with lower threshold voltage while shielding the source area;

said asymmetrical transistors being arranged into base cells such that patterns for source and drain regions formed on the relevant implant masks form a regular array which is achieved by mirroring adjacent base cells such that like regions of source or drain are directly adjacent for each pair of base cells;

wherein each base cell contains exactly one asymmetric NMOS transistor and one asymmetric PMOS transistor, each formed on an individual active area, such that the gate and vertical position of the active area are aligned between said NMOS and PMOS transistors and such that the edges of the relevant implant masks forming each of the electrical junctions adjacent to the gate are aligned with the centre of the gate.

2. The base cells of claim 1, wherein the area of the implant patterns that define the junction implants directly adjacent to the transistor gate exceeds 50% of the minimum area required for a viable implant in the CMOS process technology.

3. A plurality of base cells according to claim 1 with identical implant patterns differing only by the width of the NMOS and PMOS transistors as well as by the configuration of the gate connection.

4. A pair of tap cells having the same size and type of implant opening for the implant defining the transistor junctions directly adjacent to the transistor gates according to claim 1, wherein one of the pair of tap cells is used for the source side, and the other of the pair of tap cells is used for the drain side, said pair of tap cells containing a source-drain implant of opposite type to that of the junction directly adjacent to the transistor gate and forming an ohmic connection to the transistor bulk.