INJECTION-LOCKED PHASE LOCKED LOOP CIRCUITS USING DELAY LOCKED LOOPS

• US 20150213873A1
• Filed: 12/02/2014
• Published: 07/30/2015
• Est. Priority Date: 01/28/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: BAE, Seung-Jun, SOHN, Young-Soo, SONG, Ho-Sung, JOO, Hye-Yoon, IHM, Jeong-Don
• Granted Patent: US 9,461,656 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/083 the reference signal being additionally directly applied to the generator
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.

Claims

1. An injection-locked phase-locked loop (ILPLL) circuit, comprising:

a delay-locked loop (DLL) configured to generate a DLL clock by performing a delay-locked operation on a reference clock; and

an ILPLL including a voltage controlled oscillator (VCO), the ILPLL being configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock, wherein

the DLL clock is injected into the VCO as an injection clock of the VCO.

2. The ILPLL circuit of claim 1, wherein the DLL comprises:

a phase detector configured to generate a first phase detection signal by comparing phases of the reference clock and the DLL clock;

a first charge pump and a first loop filter configured to generate a delay-controlled voltage in response to the first phase detection signal; and

a voltage-controlled delay line configured to output the DLL clock by delaying the reference clock in response to the delay-controlled voltage.

3. The ILPLL circuit of claim 2, wherein the ILPLL comprises:

a phase frequency detector configured to generate a second phase detection signal by comparing phases of the reference clock and the output clock;

a second charge pump and a second loop filter configured to generate an oscillation-controlled voltage in response to the second phase detection signal; and

wherein

the VCO is configured to output the output clock in response to the oscillation-controlled voltage and the injection clock.

4. The ILPLL circuit of claim 3, wherein a length of a wire between the VCO and the phase frequency detector is the same as a length of a wire between the voltage-controlled delay line and the phase detector.

5. The ILPLL circuit of claim 3, wherein a length of a wire between an input terminal that receives the reference clock and the phase frequency detector is the same as a length of a wire between the input terminal that receives the reference clock and the phase detector.

6. The ILPLL circuit of claim 3, further comprising:

an output clock delay circuit between the VCO and the phase frequency detector; and

an injection clock delay circuit between the voltage-controlled delay line and the phase detector;

wherein

delays of the output clock delay circuit and the injection clock delay circuit are the same.

7. The ILPLL circuit of claim 6, wherein the output clock delay circuit is a divider including n flip-flops having m logic circuit stages, and the injection clock delay circuit includes m*n inverters connected in series.

8. The ILPLL circuit of claim 3, further comprising:

a first reference clock delay circuit between an input terminal that receives the reference clock and the phase frequency detector; and

a second reference clock delay circuit between the input terminal that receives the reference clock and the phase detector;

wherein

delays of the first reference clock delay circuit and the second reference clock delay circuit are the same.

9. A semiconductor memory device, comprising:

a memory core including a plurality of memory cells;

a control circuit configured to write data to, and read data stored in, the plurality of memory cells in response to command and address signals; and

an internal clock generation circuit configured to generate an internal clock for operation of the semiconductor memory device, the internal clock generation circuit including,

a delay-locked loop (DLL) configured to generate a DLL clock by performing a delay-locked operation on a reference clock, and

an injection-locked phase-locked loop (ILPLL) including a voltage-controlled oscillator (VCO), the ILPLL being configured to generate the internal clock by performing an injection synchronous phase-locked operation on the reference clock, and the DLL clock being injected into the VCO as an injection clock of the VCO.

10. The device of claim 9, wherein the DLL comprises:

a phase detector configured to generate a first phase detection signal by comparing phases of the reference clock and the DLL clock;

a first charge pump and a first loop filter configured to generate a delay-controlled voltage in response to the first phase detection signal; and

a voltage-controlled delay line configured to output the DLL clock by delaying the reference clock in response to the delay-controlled voltage.

11. The device of claim 10, wherein the ILPLL comprises:

a phase frequency detector configured to generate a second phase detection signal by comparing phases of the reference clock and the internal clock;

a second charge pump and a second loop filter configured to generate an oscillation-controlled voltage in response to the second phase detection signal; and

wherein

the VCO is configured to output the internal clock in response to the oscillation-controlled voltage and the injection clock.

12. The device of claim 11, wherein a length of a wire between the VCO and the phase frequency detector is the same as a length of a wire between the voltage-controlled delay line and the phase detector.

13. The device of claim 11, further comprising:

an output clock delay circuit between the VCO and the phase frequency detector; and

an injection clock delay circuit between the voltage-controlled delay line and the phase detector, delays of the output clock delay circuit and the injection clock delay circuit being the same.

14. The device of claim 13, wherein the output clock delay circuit is a divider including n flip-flops having m logic circuit stages, and the injection clock delay circuit includes m*n inverters connected in series.

15. The device of claim 9, wherein the semiconductor memory device is a dynamic random access memory (DRAM).

16. An injection-locked phase-locked loop (ILPLL) circuit, comprising:

a delay-locked loop (DLL) configured to generate a DLL clock based on a reference clock; and

a voltage controlled oscillator configured to generate an output clock based on the DLL clock and an oscillation controlled voltage, the oscillation controlled voltage being generated based on the reference clock and the output clock, and a phase of the output clock being aligned with a phase of the DLL clock.

17. The ILPLL circuit of claim 16, wherein the DLL comprises:

a phase detector configured to generate a phase detection signal based on a comparison between phases of the reference clock and the DLL clock;

a charge pump and loop filter circuit configured to generate a delay-controlled voltage based on the phase detection signal; and

a voltage-controlled delay line configured to generate the DLL clock by delaying the reference clock based on the delay-controlled voltage.

18. The ILPLL circuit of claim 16, wherein the ILPLL comprises:

a phase frequency detector configured to generate a phase detection signal based on a comparison between phases of the reference clock and the output clock; and

a charge pump and loop filter circuit configured to generate the oscillation-controlled voltage based on the phase detection signal.

19. The ILPLL circuit of claim 16, wherein the DLL comprises:

a reference clock delay circuit configured to delay the reference clock to generate a delayed reference clock;

an injection clock delay circuit configured to delay the DLL clock to generate a delayed DLL clock;

a phase detector configured to generate a phase detection signal based on a comparison between phases of the delayed reference clock and the delayed DLL clock;

a charge pump and loop filter circuit configured to generate a delay-controlled voltage based on the phase detection signal; and

a voltage-controlled delay line configured to generate the DLL clock by delaying the reference clock based on the delay-controlled voltage.

20. The ILPLL circuit of claim 16, further comprising:

a reference clock delay circuit configured to delay the reference clock to generate a delayed reference clock;

an output clock delay circuit configured to delay the output clock to generate a delayed output clock;

a phase frequency detector configured to generate a phase detection signal based on a comparison between phases of the delayed reference clock and the delayed output clock; and

a charge pump and loop filter circuit configured to generate the oscillation-controlled voltage based on the phase detection signal.