WRITING DATA TO A MEMORY CELL
First Claim
1. A circuit comprising:
- a first transistor having a threshold voltage value, a first terminal, a second terminal, and a third terminal;
a capacitive component having a first capacitive terminal and a second capacitive terminal;
a second transistor having a first terminal, a second terminal, and a third terminal; and
a data line,whereinthe first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor;
the second terminal of the first transistor is configured to receive a second-terminal voltage value;
the third terminal of the first transistor is configured to receive a third-terminal voltage value;
the first terminal of the second transistor is coupled with the data line;
the third terminal of the second transistor is configured to receive a second-transistor control signal; and
the first transistor is configured to be on and off to maintain the data line at a data line voltage value.
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Accused Products
Abstract
A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value.
13 Citations
20 Claims
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1. A circuit comprising:
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a first transistor having a threshold voltage value, a first terminal, a second terminal, and a third terminal; a capacitive component having a first capacitive terminal and a second capacitive terminal; a second transistor having a first terminal, a second terminal, and a third terminal; and a data line, wherein the first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor; the second terminal of the first transistor is configured to receive a second-terminal voltage value; the third terminal of the first transistor is configured to receive a third-terminal voltage value; the first terminal of the second transistor is coupled with the data line; the third terminal of the second transistor is configured to receive a second-transistor control signal; and the first transistor is configured to be on and off to maintain the data line at a data line voltage value. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit comprising:
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a data line; a first transistor having a threshold voltage value, a first terminal, a second terminal, and a third terminal; and a capacitive device having a first capacitive terminal and a second capacitive terminal, wherein the first terminal of the first transistor is coupled with the data line and a first terminal of the capacitive device; the second terminal of the first transistor is configured to receive a second-terminal voltage value; the third terminal of the first transistor is configured to receive a third-terminal voltage value; and the data line is configured to be clamped at a voltage value based on the threshold voltage value, the second-terminal voltage value, the third terminal voltage value, and a voltage value at the second capacitive terminal. - View Dependent Claims (9, 10, 11)
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12. A method based on a node, comprising:
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applying a first logical value to a second terminal of a capacitive component; and causing the second terminal of the capacitive component to transition from the first logical value to a second logical value different from the first logical value, wherein a first terminal of the capacitive component is coupled to the node and a first terminal of a first transistor; a second terminal of the first transistor receives a second-terminal voltage value; a third terminal of the first transistor receives a third-terminal voltage value; and a threshold voltage value of the first transistor, the second-terminal voltage value; and
the third-terminal voltage value cause the first transistor to be on and off such that the node is substantially at a node voltage value. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification