PROCESSES AND SYSTEMS FOR ENGINEERING A BARRIER SURFACE FOR COPPER DEPOSITION

• US 20150214093A1
• Filed: 03/31/2015
• Published: 07/30/2015
• Est. Priority Date: 08/31/2005
• Status: Abandoned Application

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Dordi, Yezdi, Boyd, John, Arunagiri, Tiruchirapalli, Redeker, Fritz C., Thie, William, Howald, Arthur M.
• Application Number:
  US14/675,698
• Publication Number:
  US 20150214093A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: C23C 18/1632 Features specific for the apparatus, e.g. layout of cells and of its equipment, multiple cells
• CPC Class Codes: C23C 18/1651 Two or more layers only obtained by electroless plating
• CPC Class Codes: C23C 18/1844 with use of organic or inorganic compounds other than metals, first
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/02068 during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
• CPC Class Codes: H01L 21/02074 the processing being a planarization of conductive layers
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/67161 characterized by the layout of the process chambers
• CPC Class Codes: H01L 21/67207 comprising a chamber adapted to a particular process
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76862 : Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
• CPC Class Codes: H01L 21/76867 : characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76871 : Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76879 : by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288

Abstract

A method for processing an interconnect structure on a substrate is provided, including: depositing a metallic barrier layer to line the interconnect structure, the metallic barrier layer configured to prevent diffusion of copper into the dielectric layer; depositing a thin copper seed layer over the metallic barrier layer in the interconnect structure; depositing a gap-fill copper layer over the thin copper seed layer; removing copper overburden and metallic barrier overburden, wherein removing copper overburden and metallic barrier overburden creates a planarized copper surface on the gap-fill copper layer; selectively depositing a thin layer of a cobalt-containing material on the reduced planarized copper surface; wherein the substrate is processed and transferred in controlled environments to minimize exposure to oxygen, the controlled environments defined by one or more controlled ambient environments and/or one or more vacuum environments.

Claims

1. A method for processing an interconnect structure on a substrate, comprising:

depositing a metallic barrier layer to line the interconnect structure, wherein the metallic barrier layer is deposited on an exposed surface of an underlying metal and on sidewalls of the interconnect structure defined from a dielectric layer and an etch stop layer, the metallic barrier layer configured to prevent diffusion of copper into the dielectric layer, wherein the metallic barrier layer includes Ta, TaN, Ru, or a combination thereof;

depositing a thin copper seed layer over the metallic barrier layer in the interconnect structure;

depositing a gap-fill copper layer over the thin copper seed layer;

removing copper overburden and metallic barrier overburden, wherein removing copper overburden and metallic barrier overburden creates a planarized copper surface on the gap-fill copper layer;

selectively depositing a thin layer of a cobalt-containing material on the reduced planarized copper surface, the thin layer of cobalt-containing material being configured to inhibit electromigration of the gap-fill copper layer;

wherein the substrate is processed and transferred in controlled environments to minimize exposure to oxygen, the controlled environments defined by one or more controlled ambient environments and/or one or more vacuum environments.

2. The method of claim 1, further comprising:

reducing a surface of the metallic barrier layer to convert metallic barrier oxide on the surface of the metallic barrier layer to make the surface of the metallic barrier layer to be metal-rich, the metal-rich surface providing a catalytic surface for the deposition of the thin copper seed layer, wherein reducing the surface of the metallic barrier layer is performed by a hydrogen-containing plasma.

3. The method of claim 1, further comprising:

cleaning the exposed surface of the underlying metal, wherein cleaning the exposed surface of the underlying metal removes surface metal oxide;

wherein cleaning the exposed surface of the surface metal oxide is accomplished by using one of an Ar sputtering process or a plasma process using a fluorine-containing gas, wherein the fluorine-containing gas is NF₃, CF₄, or a combination of both.

4. The method of claim 1, wherein depositing the metallic barrier layer includes depositing a first metallic barrier layer having a thickness between about 10 angstroms to about 150 angstroms, and depositing a second metallic barrier layer having a thickness between about 10 angstroms to about 50 angstroms.

5. The method of claim 4,

wherein the first metallic barrier layer is a thin tantalum nitride (TaN) layer providing conformal coverage over the interconnect structure;

and

wherein the second metallic barrier layer is a thin tantalum (Ta) layer promoting adhesion to the copper seed layer.

6. The method of claim 5,

wherein depositing the first metallic barrier layer is performed by an atomic layer deposition (ALD) process;

and

wherein depositing the second metallic barrier layer is performed by a physical vapor deposition (PVD) process or an ALD process.

7. The method of claim 1, further comprising:

after removing the copper overburden and metallic barrier overburden, and before selectively depositing the thin layer of cobalt-containing material, removing metal-organic complex contaminants and metal oxides from the substrate surface, removing organic contaminants from the substrate surface, and reducing the planarized copper surface that is removed of metal-organic complex contaminants, metal oxides, and organic contaminants.

8. The method of claim 7, wherein the metal-organic complex contaminants include copper-benzotrizole (Cu-BTA) complex.

9. The method of claim 8, wherein removing metal-organic complex contaminants is performed by using a wet clean with a cleaning solution containing tetramethylammonium hydroxide (TMAH) or complexing amines

10. The method of claim 7, wherein removing metal oxides is performed by using a wet clean with a cleaning solution containing citric acid.

11. The method of claim 7, wherein removing organic contaminants is performed by an oxygen plasma process with process temperature less than about 120°

C. to prevent forming a thick copper oxide layer on the copper surface.

12. The method of claim 1, wherein the cobalt-containing material is selected from the group consisting of CoWP, CoWB, and CoWBP.

13. The method of claim 1, wherein removing the copper overburden and metallic barrier overburden is performed by a chemical mechanical polishing (CMP) process that exposes a top surface of the dielectric layer in which the interconnect structure was etched.

14. The method of claim 1,

wherein depositing the metallic barrier layer is performed by a physical vapor deposition process;

and

wherein depositing the gap-fill copper layer is performed by an electrochemical plating (ECP) process.

15. A method for processing an interconnect structure on a substrate, comprising:

cleaning an exposed surface of an underlying metal at a bottom of the interconnect structure, wherein cleaning the exposed surface of the underlying metal removes surface metal oxide, wherein cleaning the exposed surface of the surface metal oxide is accomplished by using one of an Ar sputtering process or a plasma process using a fluorine-containing gas, wherein the fluorine-containing gas is NF₃, CF₄, or a combination of both;

depositing a metallic barrier layer to line the interconnect structure, wherein the metallic barrier layer is deposited on the exposed surface of the underlying metal and on sidewalls of the interconnect structure defined from a dielectric layer and an etch stop layer, the metallic barrier layer configured to prevent diffusion of copper into the dielectric layer, wherein the metallic barrier layer includes Ta, TaN, Ru, or a combination thereof;

reducing a surface of the metallic barrier layer to convert metallic barrier oxide on the surface of the metallic barrier layer to make the surface of the metallic barrier layer to be metal-rich, the metal-rich surface providing a catalytic surface for the deposition of the thin copper seed layer, wherein reducing the surface of the metallic barrier layer is performed by a hydrogen-containing plasma;

depositing a thin copper seed layer over the metallic barrier layer in the interconnect structure;

depositing a gap-fill copper layer over the thin copper seed layer;

removing copper overburden and metallic barrier overburden, wherein removing copper overburden and metallic barrier overburden creates a planarized copper surface on the gap-fill copper layer;

selectively depositing a thin layer of a cobalt-containing material on the reduced planarized copper surface, the thin layer of cobalt-containing material being configured to inhibit electromigration of the gap-fill copper layer;

wherein the substrate is processed and transferred in controlled environments to minimize exposure to oxygen, the controlled environments defined by one or more controlled ambient environments and/or one or more vacuum environments.

16. The method of claim 15, wherein depositing the metallic barrier layer includes depositing a first metallic barrier layer having a thickness between about 10 angstroms to about 150 angstroms, and depositing a second metallic barrier layer having a thickness between about 10 angstroms to about 50 angstroms;

wherein the first metallic barrier layer is a thin tantalum nitride (TaN) layer providing conformal coverage over the interconnect structure; and

wherein the second metallic barrier layer is a thin tantalum (Ta) layer promoting adhesion to the copper seed layer;

wherein depositing the first metallic barrier layer is performed by an atomic layer deposition (ALD) process; and

wherein depositing the second metallic barrier layer is performed by a physical vapor deposition (PVD) process or an ALD process.

17. The method of claim 15, further comprising:

after removing the copper overburden and metallic barrier overburden, and before selectively depositing the thin layer of cobalt-containing material, removing metal-organic complex contaminants and metal oxides from the substrate surface, removing organic contaminants from the substrate surface, and reducing the planarized copper surface that is removed of metal-organic complex contaminants, metal oxides, and organic contaminants;

wherein the metal-organic complex contaminants include copper- benzotrizole (Cu-BTA) complex;

wherein removing metal-organic complex contaminants is performed by using a wet clean with a cleaning solution containing tetramethylammonium hydroxide (TMAH) or complexing amines;

wherein removing metal oxides is performed by using a wet clean with a cleaning solution containing citric acid;

wherein removing organic contaminants is performed by an oxygen plasma process with process temperature less than about 120°

C. to prevent forming a thick copper oxide layer on the copper surface.

18. The method of claim 15, wherein the cobalt-containing material is selected from the group consisting of CoWP, CoWB, and CoWBP.

19. The method of claim 15, wherein removing the copper overburden and metallic barrier overburden is performed by a chemical mechanical polishing (CMP) process that exposes a top surface of the dielectric layer in which the interconnect structure was etched.

20. The method of claim 15,

wherein depositing the metallic barrier layer is performed by a physical vapor deposition process;

and

wherein depositing the gap-fill copper layer is performed by an electrochemical plating (ECP) process.