APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME

• US 20150214107A1
• Filed: 04/06/2015
• Published: 07/30/2015
• Est. Priority Date: 06/02/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Freeman, Eric H., Smith, Michael A.
• Granted Patent: US 9,466,531 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

Claims

1. A method of forming a semiconductor structure, comprising:

forming a stack of N sets, each set of the N sets comprising an insulating material and a conductive material, N being an even number equal to or greater than 8, a topmost set of the N sets being defined as an Nth set, each of the N sets including a first region and a second region, the first regions of the N sets being vertically aligned with one another, the second regions of the N sets being vertically aligned with one another;

removing the second region of the Nth set to expose the second region of an (N−

1)th set;

removing insulating material and conductive material from an upper portion of the N sets to produce a first intermediate structure in which steps in the first region of the N sets are formed respectively by (N−

i)th sets, and steps in the second region of the N sets are formed respectively by (N−

j)th sets, i being an even number inclusive of 0, j being an odd number;

forming and patterning a chop mask over the first intermediate structure to cover respective first portions of the steps in the first and second regions of the N sets while leaving respective second portions of the steps in the first and second regions of the N sets uncovered; and

removing insulating material and conductive material from the respective second portions of the steps in the first and second regions of the N sets of the first intermediate structure to form steps in a lower portion of the N sets.

2. The method of claim 1, wherein removing insulating material and conductive material from an upper portion of the N sets comprises:

forming a stair-step mask over the first region and the second region of the N sets;

recessing the stair-step mask to expose one stair-width of the N sets;

removing exposed portions of the insulating material and the conductive material in the first region and in the second region of the N sets; and

repeating the recessing the stair-step mask and removing exposed portions of the insulating material and the conductive material.

3. The method of claim 2, wherein removing exposed portions of the insulating material and the conductive material in the first region and in the second region of the N sets comprises performing two etch cycles, one etch cycle of the two etch cycles to remove the exposed portion of the insulating material and another etch cycle of the two etch cycles to remove the exposed portion of the conductive material.

4. The method of claim 1, wherein removing insulating material and conductive material from the respective second portions of the steps in the first and second regions of the N sets of the first intermediate structure to form steps in a lower portion of the N sets comprises forming steps in the lower portion of the N sets that are laterally adjacent to steps in the upper portion of the N sets.

5. The method of claim 1, wherein forming and patterning a chop mask over the first intermediate structure to cover respective first portions of the steps in the first and second regions of the N sets while leaving respective second portions of the steps in the first and second regions of the N sets uncovered comprises covering a laterally central region of the steps with the chop mask and uncovering laterally outer regions of the steps.

6. The method of claim 1, wherein forming a stack of N sets, each set of the N sets comprising an insulating material and a conductive material comprises forming conductive word line plates of a vertical memory device separated by volumes of the insulating material.

7. The method of claim 1, wherein removing insulating material and conductive material from an upper portion of the N sets comprises removing the insulating material and the conductive material from an upper half of the N sets, and wherein removing insulating material and conductive material from the respective second portions of the steps in the first and second regions of the N sets of the first intermediate structure to form steps in a lower portion of the N sets comprises forming steps in a lower half of the N sets.

8. A method of forming a semiconductor structure, comprising:

forming a first mask over a first region of stacked sets of alternating conductive material and insulating material;

exposing a second region of the stacked sets laterally adjacent to the first region;

removing exposed portions of the conductive material and insulating material from the second region of the stacked sets;

forming stair-step structures in the first region and the second region of the stacked sets, comprising;

forming a second mask over the first region and the second region of the stacked sets;

recessing the second mask to expose one stair-width of the stacked sets;

removing exposed portions of the conductive material and insulating material from the first and second regions of the stacked sets; and

repeating the recessing the second mask and removing exposed portions of the conductive material and insulating material;

forming a third mask over a first portion of the first region of the stacked sets and a first portion of the second region of the stacked sets;

exposing a second portion of the first region of the stacked sets and a second portion of the second region of the stacked sets laterally adjacent to the first portions of the first region and second region of the stacked sets; and

removing exposed portions of the conductive material and insulating material from the second portions of the first region and second region of the stacked sets.

9. The method of claim 8, wherein recessing the second mask to expose one stair-width of the stacked sets comprises recessing the second mask to expose the stacked sets at a width between about 100 nm and about 500 nm.

10. The method of claim 8, wherein removing exposed portions of the conductive material and insulating material from the second region of the stacked sets comprises anisotropically removing the conductive material and insulating material in the second region of the stacked sets.

11. The method of claim 8, further comprising removing the first mask from over the first region of the stacked sets prior to forming stair-step structures in the first region and the second region of the stacked sets.

12. The method of claim 8, wherein removing exposed portions of the conductive material and insulating material from the second portions of the first region and second region of the stacked sets comprises forming stair-step structures in the respective second portions of the first region and second region of the stacked sets that are closer to a substrate underlying the stacked sets than stair-step structures in the respective first portions of the first region and second region of the stacked sets.

13. The method of claim 8, wherein removing exposed portions of the conductive material and insulating material from the second region of the stacked sets comprises removing the exposed portion of the conductive material and the insulating material from the second region of the topmost set.

14. The method of claim 8, wherein removing exposed portions of the conductive material and insulating material from the second region of the stacked sets comprises removing the exposed portion of the conductive material and the insulating material from the second region of a plurality of sets of the stacked sets.

15. An apparatus, comprising:

two stair-step structures comprising contact regions of adjacent stacks of sets of conductive materials and insulating materials, the two stair-step structures located at respective edges of the adjacent stacks, the two stair-step structures facing each other to define a valley between the two stair-step structures, wherein each stair-step structure of the two stair-step structures comprises;

a first region comprising first contact regions to a first group of conductive materials of the respective stack; and

a second region laterally adjacent to the first region and comprising second contact regions to a second group of conductive materials of the respective stack, the second contact regions being vertically offset from the first contact regions.

16. The apparatus of claim 15, further comprising a dielectric material disposed in the valley between the two stair-step structures.

17. The apparatus of claim 16, further comprising conductive contacts extending through the dielectric material to the first contact regions and to the second contact regions of each stair-step structure of the two stair-step structures.

18. The apparatus of claim 15, wherein each stair-step structure of the two stair-step structures further comprises:

a third region comprising third contact regions to a third group of conductive materials of the respective stack, the third contact regions being vertically offset from the first contact regions and the second contact regions; and

a fourth region comprising fourth contact regions to a fourth group of conductive materials of the respective stack, the fourth contact regions being vertically offset from the first contact regions, second contact regions, and third contact regions.

19. The apparatus of claim 15, wherein the adjacent stacks of sets of conductive materials and insulating materials comprise adjacent vertical memory arrays of memory cells.

20. The apparatus of claim 19, wherein the conductive materials comprise at least one of word line connections and control gates of the vertical memory arrays of memory cells.