MULTIWIDTH FINFET WITH CHANNEL CLADDING

• US 20150214365A1
• Filed: 01/24/2014
• Published: 07/30/2015
• Est. Priority Date: 01/24/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Jacob, Ajey Poovannummoottil
• Granted Patent: US 9,954,104 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

An improved structure and methods of fabrication for finFET devices utilizing a cladding channel are disclosed. A staircase fin is formed where the fin comprises an upper portion of a first width and a lower portion of a second width, wherein the lower portion is wider than the upper portion. The narrower upper portion allows the cladding channel to be deposited and still have sufficient space for proper gate deposition, while the lower portion is wide to provide improved mechanical stability, which protects the fins during the subsequent processing steps.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate having a plurality of fins formed thereon, wherein at least one fin of the plurality of fins is comprised of a lower portion and an upper portion, wherein the lower portion has a first thickness and wherein the upper portion has a second thickness, and wherein the first thickness is greater than the second thickness, and wherein the at least one fin has a staircase profile.

2. The semiconductor structure of claim 1, further comprising a conformal cladding layer disposed on the upper portion of the at least one fin of the plurality of fins.

3. The semiconductor structure of claim 2, further comprising a dielectric layer disposed on the semiconductor structure, wherein the dielectric layer has a top surface disposed above the lower portion of the at least one fin of the plurality of fins, and below the conformal cladding layer.

4. The semiconductor structure of claim 3, wherein the conformal cladding layer is comprised of silicon germanium.

5. The semiconductor structure of claim 3, wherein the conformal cladding layer is comprised of a III-V compound.

6. The semiconductor structure of claim 5, wherein the conformal cladding layer comprises a material selected from the group consisting of indium phosphide and indium gallium arsenide.

7. The semiconductor structure of claim 4, wherein the upper portion of each fin of the plurality of fins comprises a doped region.

8. The semiconductor structure of claim 7, further comprising a diffusion barrier disposed over the doped region.

9. The semiconductor structure of claim 8, wherein the diffusion barrier comprises a carbon-doped silicon film.

10. A semiconductor structure comprising:

a semiconductor substrate having a plurality of NFET fins formed thereon and a plurality of PFET fins formed thereon, wherein each fin of the plurality of PFET fins is comprised of a lower portion and an upper portion, wherein the lower portion has a first thickness and wherein the upper portion has a second thickness, and wherein the first thickness is greater than the second thickness.

11. The semiconductor structure of claim 10, further comprising a conformal PFET cladding layer disposed on the upper portion of each fin of the plurality of PFET fins.

12. The semiconductor structure of claim 11, further comprising a dielectric layer disposed on the semiconductor structure, wherein the dielectric layer has a top surface disposed above the lower portion of each fin of the plurality of PFET fins, and below the conformal PFET cladding layer.

13. The semiconductor structure of claim 12, wherein the conformal PFET cladding layer is comprised of silicon germanium.

14. The semiconductor structure of claim 12, wherein each fin of the plurality of NFET fins is comprised of a lower portion and an upper portion, wherein the lower portion has a first thickness and wherein the upper portion has a second thickness, and wherein the first thickness is greater than the second thickness.

15. The semiconductor structure of claim 14, further comprising a conformal NFET cladding layer disposed on the upper portion of each fin of the plurality of NFET fins.

16. The semiconductor structure of claim 15, wherein the conformal NFET cladding layer is comprised of a III-V compound.

17. A method of forming a semiconductor structure, comprising:

forming an upper portion of a first set of fins;

forming hardmask material regions over the upper portion of the first set of fins;

forming a lower portion of the first set of fins;

depositing a dielectric layer over the first set of fins;

recessing the dielectric layer to expose the upper portion of the first set of fins; and

forming a first conformal cladding channel on the upper portion of the first set of fins.

18. The method of claim 17, further comprising planarizing the dielectric layer prior to the recessing step.

19. The method of claim 18, further comprising forming a second set of fins, wherein the second set of fins are uni-width fins.

20. The method of claim 18, further comprising forming a second set of fins, wherein the second set of fins are multi-width fins and, forming a second conformal cladding channel on the second set of fins.