SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20150214376A1
• Filed: 11/21/2014
• Published: 07/30/2015
• Est. Priority Date: 12/03/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koezuka, Junichi, Shima, Yukinori, Jintyou, Masami, Hamochi, Takashi, Higano, Satoshi, Yamazaki, Shunpei
• Granted Patent: US 9,991,392 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 23/53233 Copper alloys
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

To provide a novel semiconductor device which includes a transistor and a metal film containing Cu for a wiring, a signal line, or the like. The semiconductor device includes a first wiring, a second wiring, a first transistor, and a second transistor. The first wiring is electrically connected to a source or a drain of the first transistor, and the second wiring is electrically connected to a gate of the second transistor. The first wiring and the second wiring each include a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). The Cu—X alloy film in the first wiring is connected to the Cu—X alloy film in the second wiring.

Claims

1. A semiconductor device comprising:

a first transistor comprising a source and a drain; and

a second transistor comprising a gate, the gate directly connecting to one of the source and the drain,

wherein each of the source and the drain includes a first Cu—

X alloy film,

wherein the gate includes a second Cu—

X alloy film,

wherein X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti, and

wherein the first Cu—

X alloy film and the second Cu—

X alloy film are covered with an oxide film including X.

2. The semiconductor device according to claim 1, wherein each of the source and the drain has a stacked structure including the first Cu—

X alloy film, a first Cu film over the first Cu—

X alloy film, and a third Cu—

X alloy film over the first Cu film.

3. The semiconductor device according to claim 1, wherein the gate has a stacked structure including the second Cu—

X alloy film, a second Cu film over the second Cu—

X alloy film, and a fourth Cu—

X alloy film over the second Cu film.

4. The semiconductor device according to claim 1,

wherein each of the source and the drain has a first stacked structure including the first Cu—

X alloy film, a first Cu film over the first Cu—

X alloy film, and a third Cu—

X alloy film over the first Cu film, and

wherein the gate has a second stacked structure including the second Cu—

X alloy film, a second Cu film over the second Cu—

X alloy film, and a fourth Cu—

X alloy film over the second Cu film.

5. The semiconductor device according to claim 1, wherein X is Mn.

6. The semiconductor device according to claim 1, wherein an inclination angle between a surface on which one of the source, the drain, and the gate is formed and a side surface of the one of the source, the drain, and the gate is greater than or equal to 30°

and less than or equal to 70°

.

7. A display device comprising the semiconductor device according to claim 1.

8. A semiconductor device comprising:

a first transistor comprising a source and a drain; and

a second transistor comprising a gate, the gate directly connecting to one of the source and the drain,

wherein each of the source and the drain has a first stacked structure including a first Cu—

X alloy film,

wherein the gate includes a second Cu—

X alloy film, and

wherein X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti.

9. The semiconductor device according to claim 8, wherein the first stacked structure further includes a first Cu film over the first Cu—

X alloy film and a third Cu—

X alloy film over the first Cu film.

10. The semiconductor device according to claim 9, wherein the gate has a second stacked structure including the second Cu—

X alloy film, a second Cu film over the second Cu—

X alloy film, and a fourth Cu—

X alloy film over the second Cu film.

11. The semiconductor device according to claim 8, wherein X is Mn.

12. The semiconductor device according to claim 8, wherein an inclination angle between a surface on which one of the source, the drain, and the gate is formed and a side surface of the one of the source, the drain, and the gate is greater than or equal to 30°

and less than or equal to 70°

.

13. A display device comprising the semiconductor device according to claim 8.

19. A display device comprising the semiconductor device according to claim 8.

14. A semiconductor device comprising:

a first transistor comprising a source and a drain; and

a second transistor comprising a gate, the gate directly connecting to one of the source and the drain,

wherein each of the source and the drain includes a first Cu—

X alloy film,

wherein the gate has a first stacked structure including a second Cu—

X alloy film, and

wherein X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti.

15. The semiconductor device according to claim 14, wherein the first stacked structure further includes a first Cu film over the second Cu—

X alloy film and a third Cu—

X alloy film over the first Cu film.

16. The semiconductor device according to claim 15, wherein each of the source and the drain has a second stacked structure including the first Cu—

X alloy film, a second Cu film over the first Cu—

X alloy film, and a fourth Cu—

X alloy film over the second Cu film.

17. The semiconductor device according to claim 14, wherein X is Mn.

18. The semiconductor device according to claim 14, wherein an inclination angle between a surface on which one of the source, the drain, and the gate is formed and a side surface of the one of the source, the drain, and the gate is greater than or equal to 30°

and less than or equal to 70°

.