SEMICONDUCTOR CIRCUIT

• US 20150214732A1
• Filed: 04/03/2015
• Published: 07/30/2015
• Est. Priority Date: 05/13/2013
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: HARUKI, Satoshi, KATO, Kazuhiro
• Application Number:
  US14/678,311
• Publication Number:
  US 20150214732A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02H 9/042 comprising means to limit the absorbed power or indicate damaged over-voltage protection device
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

A semiconductor circuit includes a clamp circuit and a switch circuit connected in series between a first power source terminal and a second power source terminal. The clamp circuit is configured to connect the first power source terminal to the second power source terminal when a voltage difference between the first and second power source terminals exceeds a threshold value. A control circuit controls the switch circuit such that the switch circuit is not conductive (open) when the voltage difference between the power source terminals is constant and is conductive (closed) when the voltage difference between the first and second power source terminals changes by more than a predetermined magnitude.

Claims

1. A semiconductor circuit comprising:

an internal circuit connected between a first power source line and a second power source line;

a clamp circuit connected between the first power source line and the second power source line, the clamp circuit performing a clamp operation when turned on;

a control circuit configured to output a control signal in response to a voltage fluctuation between the first power source line and the second power source line; and

a switch unit configured to switch on-off the clamp circuit in response to the control signal.

2. The semiconductor circuit according to claim 1, wherein the clamp operation is performed by electrically connecting the first power source line and the second power source line.

3. The semiconductor circuit according to claim 1, wherein the control circuit outputs the control signal when a voltage between the first power source line and the second power source line exceeds a predetermined threshold voltage.

4. The semiconductor circuit according to claim 1, wherein

the clamp circuit includes:

a trigger circuit configured to output a trigger signal in response to a voltage between the first power source line and the second power source line; and

a clamp element, a main current path of which is connected between the first power source line and the second power source line and which is controlled on-off by the trigger signal, and

the switch unit turns on or off the clamp element in response to the control signal.

5. The semiconductor circuit according to claim 3, wherein the clamp element includes a first transistor, a control electrode of which is connected to the switch unit.

6. The semiconductor circuit according to claim 4, wherein the trigger circuit includes a first RC circuit including a capacitor and a resistor.

7. The semiconductor circuit according to claim 5, wherein the clamp circuit includes a buffer circuit configured to supply an output signal to the control electrode of the first transistor in response to a trigger signal.

8. The semiconductor circuit according to claim 5, wherein the switch unit includes a second transistor, a main current path of which is connected between the control electrode of the first transistor and the second power source line, and a control electrode of which receives the control signal.

9. The semiconductor circuit according to claim 1, wherein the control circuit includes a series circuit of a diode and a resistor, the diode is reverse-biased by a voltage applied between the first power source line and the second power source line when the internal circuit is in a steady-state condition, and the control circuit outputs the control signal by conduction of the diode when the voltage between the first power source line and the second power source line exceeds a predetermined threshold voltage.

10. The semiconductor circuit according to claim 3, wherein the control circuit includes a series circuit of a diode and a resistor, the diode is reverse-biased by a voltage applied between the first power source line and the second power source line when the internal circuit is in a steady-state condition, and the control circuit outputs the control signal by conduction of the diode when the voltage between the first power source line and the second power source line exceeds a predetermined threshold voltage.

11. The semiconductor circuit according to claim 4, wherein the control circuit includes a series circuit of a diode and a resistor, the diode is reverse-biased by a voltage applied between the first power source line and the second power source line when the internal circuit is in a steady-state condition, and the control circuit outputs the control signal by conduction of the diode when the voltage between the first power source line and the second power source line exceeds a predetermined threshold voltage.

12. The semiconductor circuit according to claim 8, wherein

each of the first transistor and the second transistor includes an NMOS transistor, and

a main current path of the second transistor is connected between the second power source line and a gate electrode of the first transistor.

13. The semiconductor circuit according to claim 8, wherein

each of the first transistor and the second transistor includes a PMOS transistor, and

a main current path of the second transistor is connected between the first power source line and a gate electrode of the first transistor.

14. The semiconductor circuit according to claim 9, wherein the control circuit outputs the control signal from a connection node between the diode and the resistor.

15. A semiconductor circuit comprising:

a first power source line to which a high potential voltage is applied;

a second power source line to which a low potential voltage is applied;

an internal circuit connected between the first power source line and the second power source line;

a CR circuit connected between the first power source line and the second power source line;

a first transistor having a main current path connected between the first power source line and the second power source line and having a control electrode that receives a signal from the CR circuit;

a control circuit configured to be connected between the first power source line and the second power source line and output a control signal when a voltage between the first power source line and the second power source line exceeds a predetermined threshold voltage; and

a second transistor having a main current path connected between the first power source line and the control electrode of the first transistor and having a control electrode that receives the control signal.

16. The semiconductor circuit according to claim 15, wherein the control circuit includes a series circuit of a diode and a resistor, the diode is reverse-biased by a voltage applied between the first power source line and the second power source line when the internal circuit is in a steady-state condition, and the control circuit outputs the control signal by conduction of the diode when the voltage between the first power source line and the second power source line exceeds the predetermined threshold voltage.

17. The semiconductor circuit according to claim 16, wherein

the first transistor is a PMOS transistor having a main current path connected between the first power source line and the second power source line, and

the second transistor is a PMOS transistor having a main current path connected between the control electrode of the first transistor and the first power source line.

18. A semiconductor circuit comprising:

a first power source line to which a high potential voltage is applied;

a second power source line to which a low potential voltage is applied;

an internal circuit connected between the first power source line and the second power source line;

a CR circuit connected between the first power source line and the second power source line;

a first transistor having a main current path connected between the first power source line and the second power source line and having a control electrode that receives a signal from the CR circuit;

a control circuit configured to be connected between the first power source line and the second power source line and output a control signal when a voltage between the first power source line and the second power source line exceeds a predetermined threshold voltage; and

a second transistor having a main current path connected between the control electrode of the first transistor and the second power source line, and having a control electrode that receives the control signal.

19. The semiconductor circuit according to claim 18, wherein the control circuit includes a series circuit of a diode and a resistor, the diode is reverse-biased by a voltage applied between the first power source line and the second power source line when the internal circuit is in a steady-state condition, and the control circuit outputs the control signal by conduction of the diode when the voltage between the first power source line and the second power source line exceeds the predetermined threshold voltage.

20. The semiconductor circuit according to claim 19, wherein

the first transistor is an NMOS transistor having a main current path connected between the first power source line and the second power source line, and

the second transistor is an NMOS transistor having a main current path connected between the control electrode of the first transistor and the second power source line.