APPARATUS, METHOD AND SYSTEM FOR ASYMMETRIC, FULL-DUPLEX COMMUNICATION

• US 20150215105A1
• Filed: 01/27/2014
• Published: 07/30/2015
• Est. Priority Date: 01/27/2014
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Agrawal, Vinayak, Sharma, Namrta, Velitheri, Rahul, Tirunagari, Prashanth, Manchikalapudi, Manjusha
• Granted Patent: US 9,240,878 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04B 1/56 with provision for simultaneous communication in two directions
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex

Abstract

Techniques and methods for performing asymmetric, full-duplex communication via a signal line. In an embodiment, a transceiver includes transmit circuitry to transmit a first signal via a node coupled to a signal line, where the first signal is transmitted concurrently with the transceiver receiving a second signal via the node at a substantially different data rate than that of the first signal. In another embodiment, signal processing circuitry of the transceiver detects a composite signal at the node, the composite signal including a combination of the first signal and the second signal. Based on the combination of the first signal and the second signal, the signal processing circuitry generates a processed signal, including the signal processing circuitry reducing a contribution by the first signal. The processed signal is provided to receiver circuitry of the transceiver.

Claims

1. A first device comprising:

a first transceiver configured to perform, with a second device coupled to the first device, asymmetric full-duplex communication of a first signal and a second signal, the first transceiver including;

first transmitter circuitry configured to transmit the first signal from the first device via a first node while the second device transmits the second signal to the first node, wherein the first node includes a combination of the first signal and the second signal;

signal processing circuitry coupled to the first node, the signal processing circuitry configured to generate a third signal from the combination, including the signal processing circuitry to reduce a contribution by the first signal; and

first receiver circuitry coupled to receive the third signal from the signal processing circuitry.

2. The first device of claim 1, wherein a data rate differential for the first signal and the second signal is at least three-to-one.

3. The first device of claim 1, wherein one of the first signal and the second signal includes a stable portion consisting of two or more consecutive bits which each have the same logic level, wherein an exchange of the stable portion is concurrent with a transition time of the other of the first signal and the second signal.

4. The first device of claim 1, wherein a data rate of the first signal is faster than a data rate of the second signal, and, wherein a logic state transition time of the second signal is equal to or greater than a single data bit time period of the first signal.

5. The first device of claim 1, wherein the first signal is one of a first differential signal pair and wherein the second signal is one of a second differential signal pair.

6. The first device of claim 1, wherein the signal processing circuitry to reduce the contribution by the first signal includes the signal processing circuitry to band-pass filter the combination.

7. The first device of claim 6, wherein the signal processing circuitry to band-pass filter the combination includes the signal processing circuitry to low-pass filter the combination.

8. The first device of claim 1, wherein the signal processing circuitry to reduce the contribution by the first signal includes the signal processing circuitry to subtract a dummy version of the first signal from the combination.

9. A method at a first device, the method comprising:

performing asymmetric full-duplex communication with a second device coupled to the first device, including transmitting a first signal from the first device via a first node while the second device transmits a second signal to the first node, wherein the first node includes a combination of the first signal and the second signal;

with signal processing circuitry coupled to the first node, generating a third signal from the combination, including reducing a contribution by the first signal; and

providing the third signal to first receiver circuitry of the first device.

10. The method of claim 9, wherein a data rate differential for the first signal and the second signal is at least three-to-one.

11. The method of claim 9, wherein one of the first signal and the second signal includes a stable portion consisting of two or more consecutive bits which each have the same logic level, wherein an exchange of the stable portion is concurrent with a transition time of the other of the first signal and the second signal.

12. The method of claim 9, wherein a data rate of the first signal is faster than a data rate of the second signal, and, wherein a logic state transition time of the second signal is equal to or greater than a single data bit time period of the first signal.

13. The method of claim 9, wherein the first signal is one of a first differential signal pair and wherein the second signal is one of a second differential signal pair.

14. The method of claim 9, wherein reducing the contribution by the first signal includes band-pass filtering the combination.

15. The method of claim 14, wherein band-pass filtering the combination includes low-pass filtering the combination.

16. The method of claim 9, wherein reducing the contribution by the first signal includes subtracting a dummy version of the first signal from the combination.