MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM

• US 20150220394A1
• Filed: 05/16/2014
• Published: 08/06/2015
• Est. Priority Date: 02/03/2014
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: TANAKA, Hiroaki
• Application Number:
  US14/279,485
• Publication Number:
  US 20150220394A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

According to an embodiment, a controller performs a process corresponding to processing of a second command when the second command is received from a host device before a first time passes after an end of processing corresponding to a first command received from the host device, and executes patrol read to read data stored in a nonvolatile memory continuously in predetermined units when no command is received from the host device before the first time passes.

Claims

1. A memory system comprising:

a nonvolatile memory; and

a controller configured to control the nonvolatile memory, wherein

the controller is configured to

perform a process corresponding to a second command when the second command is received from a host device before a first time passes after an end of processing corresponding to a first command received from the host device, and

execute patrol read to read data stored in the nonvolatile memory continuously in predetermined units when no command is received from the host device before the first time passes.

2. The memory system according to claim 1, wherein the first time is a preset fixed time.

3. The memory system according to claim 2, wherein the controller includes a timer that counts the fixed time after the end of the processing corresponding to the first command.

4. The memory system according to claim 1, wherein

the controller has a timer that generates a signal at a predetermined interval, and

the first time is a time from the end of the processing corresponding to the first command until the signal is first generated by the timer after the end of the processing corresponding to the first command.

5. The memory system according to claim 1, wherein, from a start of the patrol read until the first time passes, the controller causes a process of the patrol read that is to be executed next to wait.

6. The memory system according to claim 1, wherein the patrol read is executed for valid data stored in the nonvolatile memory.

7. The memory system according to claim 1, wherein error correction is performed in the patrol read using an error-correcting code attached to the data.

8. The memory system according to claim 7, wherein when the data is corrected using the error-correcting code in the patrol read, the corrected data is written at a storage position different from a storage position at which the data has been stored and the original data is invalidated.

9. The memory system according to claim 1, wherein the nonvolatile memory is a NAND flash memory and the predetermined unit is a page.

10. A method of controlling a memory system including a nonvolatile memory, the method comprising:

performing a process corresponding to a second command when the second command is received from a host device before a first time passes after an end of processing corresponding to a first command received from the host device, and

executing patrol read to read data stored in the nonvolatile memory continuously in predetermined units when no command is received from the host device before the first time passes.

11. The method of controlling a memory system according to claim 10, wherein the first time is a preset fixed time.

12. The method of controlling a memory system according to claim 10, wherein the first time is a time from the end of the processing corresponding to the first command until a signal is first generated from an output of a timer that generates the signal at a predetermined interval after the end of the processing corresponding to the first command.

13. The method of controlling a memory system according to claim 10, further comprising:

Causing, from a start of the patrol read until the first time passes, a process of the patrol read that is to be executed next to wait.

14. The method of controlling a memory system according to claim 10, wherein the patrol read is executed for valid data stored in the nonvolatile memory.

15. The method of controlling a memory system according to claim 10, wherein error correction is performed in the patrol read using an error-correcting code attached to the data.

16. The method of controlling a memory system according to claim 10, wherein when the data is corrected using the error-correcting code in the patrol read, the corrected data is written at a storage position different from a storage position at which the data has been stored and the original data is invalidated.

17. The method of controlling a memory system according to claim 10, wherein the nonvolatile memory is a NAND flash memory and the predetermined unit is a page.