METHOD, APPARATUS AND SYSTEM FOR A SOURCE-SYNCHRONOUS CIRCUIT-SWITCHED NETWORK ON A CHIP (NOC)

• US 20150220470A1
• Filed: 06/28/2013
• Published: 08/06/2015
• Est. Priority Date: 06/28/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Anders, Mark A., Kaul, Himanshu, Satpathy, Sudhir K., Krishnamurthy, Ram K., Chen, Gregory K.
• Granted Patent: US 9,652,425 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: H04L 12/46 Interconnection of networks
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a router including a first input port and a first output port, wherein the router is of a network on a chip (NoC), the router to enable communication of a packet from the router to a second router of the NoC based on transitions in control flow signals.

2. The apparatus of claim 1, wherein the first input port includes a latch to receive communication of a request from the second router, responsive to a transition in a first control flow signal received in the first input port.

3. The apparatus of claim 2, wherein the first input port is to send a second control flow signal to the second router responsive to servicing of the request to indicate readiness for servicing of another request, and to open the latch.

4. The apparatus of claim 3, wherein the second router is to communicate a plurality of packets to the router before receipt of the transition in the second control flow signal, wherein a credit level of the second router is updated based on the transition in the second control flow signal.

5. The apparatus of claim 2, wherein when closed, the latch is to prevent insertion of a new packet into the first input port during processing of the request.

6. The apparatus of claim 3, wherein the first input port is to receive a packet associated with the transition in the first flow control signal and to transition the second flow control signal to indicate readiness for receipt of another packet.

7. The apparatus of claim 4, further comprising a buffer coupled between the router and the second router to store at least one of the plurality of packets before communication to the router.

8. The apparatus of claim 1, wherein the router comprises a credit logic to receive a first control flow signal and a second control flow signal, and to generate a third signal based on the first and second control flow signals, and to update a credit level based on the first and second control flow signals and the third signal.

9. The apparatus of claim 8, wherein the third signal is a first value responsive to a transition in the first control flow signal and a second value responsive to a transition in the second control flow signal.

10. The apparatus of claim 8, wherein the credit logic is to enable the second router to communicate the request before receipt of a first transition in the second control flow signal, and to prevent the second router from communication of the request when the credit level is less than a threshold.

11. The apparatus of claim 1, wherein the NoC is a source-synchronous hybrid packet/circuit-switched NoC.

12. The apparatus of claim 1, wherein the router is to operate at a first frequency and a first voltage, and the second router is to operate at a second frequency and a second voltage.

13. An apparatus comprising:

a plurality of routers each having a set of input ports and a set of output ports, each of the input ports and the output ports having a circuit-switched portion and a packet-switched portion, wherein the packet-switched portion of a plurality of the sets of input ports and output ports between a source logic and a destination logic are to establish a circuit-switched channel between the source logic and the destination logic to communicate circuit-switched data based on control flow signal transitions, wherein the plurality of routers operate according to a source-synchronous protocol.

14. The apparatus of claim 13, wherein each of the packet-switched portions includes a buffer to store requests, wherein a priority of the requests is variable at each of the packet-switched portions.

15. The apparatus of claim 14, wherein the buffer includes a plurality of entries each to store direction information associated with one of the requests, and wherein global priority ordering is maintained by storage of a first priority request in an available entry of the buffer having a highest priority.

16. The apparatus of claim 15, further comprising:

a first selector coupled to an input of the buffer; and

a write pointer logic to control the first selector, wherein the write pointer logic includes a Gray counter to select an entry of the buffer in which to write the direction information;

a second selector coupled to an output of the buffer; and

a read pointer logic to control the first selector, wherein the read pointer logic includes a Gray counter to select an entry of the buffer from which to read the direction information.

17. The apparatus of claim 13, wherein when a first request has a highest priority in each of the packet-switched portions between the source logic and the destination logic, the circuit-switched channel is established for communication of data associated with the first request.

18. The apparatus of claim 17, wherein the circuit-switched channel is to communicate a plurality of data segments of a circuit-switched data communication responsive to establishment of the circuit-switched channel.

19. The apparatus of claim 18, wherein the circuit-switched channel is to communicate a first circuit control flow signal to indicate arrival of a first data segment of the plurality of data segments with at least one additional data segment to follow, a second circuit control flow signal to indicate completion of the circuit-switched data communication, and a third circuit control flow signal to indicate receipt of each data segment of the plurality of data packets in the source logic.

20. The apparatus of claim 13, wherein each of the plurality of routers is associated with a core of a system on a chip (SoC).

21. The apparatus of claim 13, wherein the packet-switched portion is to communicate sideband data as a first packet.

22. The apparatus of claim 20, wherein the packet-switched portion is to communicate a reservation request for establishment of the circuit-switched channel as a second packet.

23. A method comprising:

determining, in a packet portion of a network on chip (NoC), that a reservation request issued from a source logic to a destination logic has a highest priority among a plurality of reservation requests stored in buffers of a plurality of routers coupled between the source logic and the destination logic; and

establishing, in a circuit portion of the NoC, a circuit-switched channel between the source logic and the destination logic, to enable data communication between the source logic and the destination logic.

24. The method of claim 23, wherein the NoC is a source-synchronous hybrid packet/circuit-switched NoC.

25. The method of claim 23, further comprising responsive to receipt of a first packet of the data communication in the destination logic, initiating a transition in a first acknowledgement signal to be communicated to the source logic.

26. The method of claim 25, further comprising updating a credit value in the source logic responsive to receipt of the transition in the first acknowledgement signal.

27. The method of claim 26, further comprising enabling the source logic to communicate a plurality of packets to the destination logic before receipt of the transition in the first acknowledgment signal.

28. A system comprising:

a system on a chip (SoC) including a plurality of cores each associated with a router of a source-synchronous network on a chip (NoC), each of the routers comprising;

a set of input ports and a set of output ports, each of the input ports and the output ports having a circuit-switched portion and a packet-switched portion, wherein the packet-switched portions between a source core and a destination core are to establish a circuit-switched channel for communication of circuit-switched data based on control flow signal transitions; and

a non-volatile storage coupled to the SoC.

29. The system of claim 28, wherein a first packet-switched portion is to generate a transition in a first packet control flow signal to indicate transmission of a packet from the first packet-switched portion to a second packet-switched portion, and the second packet-switched portion is to generate a transition in a second packet control flow signal to indicate readiness for receipt of another packet.

30. The system of claim 29, wherein a first circuit-switched portion is to generate a transition in a first circuit control flow signal to indicate arrival of a first data segment of the circuit-switched data, and to generate a transition in a second circuit control flow signal to indicate completion of communication of the circuit-switched data.