IN-SITU STRAINING EPITAXIAL PROCESS

• US 20150221509A1
• Filed: 02/06/2014
• Published: 08/06/2015
• Est. Priority Date: 02/06/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Shih-Chieh, Jeng, Pei-Ren, Chen, Hsiu-Ting, Huang, Yi-Ming, Chen, Hsing-Chi
• Granted Patent: US 10,644,116 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method includes forming a recess in a semiconductor substrate, the recess being adjacent to a gate stack, performing an epitaxial growth process within the recess to form a straining region, and forming a defect within the straining region in-situ with the epitaxial growth process.

Claims

1. A method comprising:

providing a semiconductor substrate with a gate stack;

forming a recess in the semiconductor substrate, the recess being adjacent to the gate stack;

performing an epitaxial growth process within the recess to form a straining region; and

forming a defect within the straining region in-situ with the epitaxial growth process.

2. The method of claim 1, wherein the epitaxial growth process is performed at different rates on different sides of the recess.

3. The method of claim 1, wherein characteristics of the defect are tuned by adjusting parameters of the epitaxial growth process.

4. The method of claim 3, wherein the parameters include temperature.

5. The method of claim 3, wherein the parameters include pressure.

6. The method of claim 3, wherein the parameters include doping concentration.

7. The method of claim 3, wherein the parameters include concentration of an element with a smaller lattice constant than a material forming the substrate.

8. The method of claim 3, wherein the parameters include precursor type.

9. The method of claim 1, wherein the straining region is such that it causes a tensile strain on a channel underneath the gate stack.

10. The method of claim 1, wherein the straining region comprises a combination of silicon and an element with a smaller lattice constant.

11. The method of claim 1, wherein the straining region comprises silicon carbide.

12. The method of claim 1, wherein the straining region is doped with an n-type dopant.

13. The method of claim 1, wherein the straining region is doped with phosphorous.

14. The method of claim 1, wherein the defect comprises two dislocations that form a cross-point within the straining region.

15. A method comprising:

forming a recess in a semiconductor substrate, the recess being adjacent to a gate stack, the gate stack positioned above a channel;

performing an epitaxial growth process within the recess to form a straining region to cause a tensile strain on the channel; and

forming a defect within the straining region in-situ with the epitaxial growth process, the defect comprising at least two dislocations that form a cross-point within the straining region;

wherein a position of the cross-point is tuned by adjusting parameters of the epitaxial growth process.

16. The method of claim 15, wherein the parameters include at least one of:

temperature, pressure, doping concentration, concentration of an element with a smaller lattice constant than a material forming the substrate, and precursor type;

17. The method of claim 15, wherein the cross-point is closer to a bottom of the straining region than to a top of the straining region.

18. A semiconductor device comprising:

an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel;

wherein the straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region;

wherein the straining region comprises an element with a smaller lattice constant than a material forming the substrate.

19. The device of claim 18, wherein the straining region is doped with an n-type dopant.

20. The device of claim 18, wherein the straining region comprises silicon carbide (SiC) doped with phosphorous.