ALTERNATING OPEN-ENDED VIA CHAINS FOR TESTING VIA FORMATION AND DIELECTRIC INTEGRITY

• US 20150221567A1
• Filed: 04/17/2015
• Published: 08/06/2015
• Est. Priority Date: 05/16/2013
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Fen, Christiansen, Cathryn J., Dufresne, Roger A.
• Application Number:
  US14/689,463
• Publication Number:
  US 20150221567A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.

Claims

1. A wafer structure comprising:

integrated circuit chips;

kerf areas located between said integrated circuit chips;

via chain test structures in at least one of said kerf areas and said integrated circuit chips, said via chain test structures comprising;

a first conductor in a first area of said wafer structure;

a second conductor in a second area of said wafer structure;

first via chains connected at individual points to said first conductor, each of said first via chains comprising an open-ended electrical circuit beginning at said first conductor and ending in an insulated region of said second area of said wafer structure; and

second via chains connected at individual points to said second conductor, each of said second via chains comprising an open-ended electrical circuit beginning at said second conductor and ending in an insulated region of said first area of said wafer structure.

2. The wafer structure according to claim 1, said first via chains being electrically insulated from said second via chains.

3. The wafer structure according to claim 1, said first via chains and said second via chains comprising:

first conductive segments formed at a first layer and second conductive segments formed at a second layer, said first conductive segments and said second conductive segments being interconnected by vias and forming geometrically shaped portions.

4. The wafer structure according to claim 3, said geometrically shaped portions comprising one of:

geometric structures that alternate by type, across two or more layers of said wafer structure; and

serpentine and comb structures that alternate in type or instance, in a single layer of said wafer structure.

5. The wafer structure according to claim 1, at least one of said first conductor and said second conductor comprising an electrically conductive spine having electrical connectors protruding from a base of said electrically conductive spine.

6. The wafer structure according to claim 1, said first via chains comprising first electrical circuits beginning at said first conductor at a first location within said first area, and said second via chains comprising second electrical circuits beginning at said second conductor at a second location within said second area.

7. A structure comprising:

a first electrically conductive spine in a first area of a semiconductor wafer, said first electrically conductive spine having first electrical connectors protruding from a base of said first electrically conductive spine;

a second electrically conductive spine in a second area of said semiconductor wafer, said second electrically conductive spine having second electrical connectors protruding from a base of said second electrically conductive spine;

first via chains operatively connected to said first electrical connectors, a first via chain being operatively connected to each of said first electrical connectors, each of said first via chains comprising an open-ended electrical circuit beginning at said first electrically conductive spine and ending in an insulated region of said second area; and

second via chains operatively connected to said second electrical connectors, a second via chain being operatively connected to each of said second electrical connectors, each of said second via chains comprising an open-ended electrical circuit beginning at said second electrically conductive spine and ending in an insulated region of said first area.

8. The structure according to claim 7, said first via chains being electrically insulated from said second via chains.

9. The structure according to claim 7, said first via chains alternating with said second via chains.

10. The structure according to claim 7, said first electrical connectors protruding from said first electrically conductive spine facing said second electrical connectors protruding from said second electrically conductive spine.

11. The structure according to claim 7, said first via chains and said second via chains comprising:

first conductive segments formed at a first layer of said semiconductor wafer and second conductive segments formed at a second layer of said semiconductor wafer, said first conductive segments and said second conductive segments being interconnected by vias and forming geometrically shaped portions.

12. The structure according to claim 11, said geometrically shaped portions comprising one of:

geometric structures that alternate by type, across two or more layers of said semiconductor wafer; and

serpentine and comb structures that alternate in type or instance, in a single layer of said semiconductor wafer.

13. The structure according to claim 11, one of said first conductive segments and said second conductive segments further comprising a test tap.

14. A structure comprising:

a wafer having a top surface and a bottom surface;

integrated circuit chips located on said top surface of said wafer;

kerf areas located between said integrated circuit chips on said top surface of said wafer; and

via chain test structures located in said kerf areas, said via chain test structures comprising;

a first conductor in a first portion of said kerf areas;

a second conductor in a second portion of said kerf areas;

first via chains connected at individual points to said first conductor, each of said first via chains comprising an open-ended electrical circuit beginning at said first conductor and ending in an insulated region of said second portion of said kerf areas; and

second via chains connected at individual points to said second conductor, each of said second via chains comprising an open-ended electrical circuit beginning at said second conductor and ending in an insulated region of said first portion of said kerf areas.

15. The structure according to claim 14, said second portion of said kerf areas being adjacent to and contacting said first portion of said kerf areas.

16. The structure according to claim 14, said first via chains being electrically insulated from said second via chains.

17. The structure according to claim 14, said first via chains and said second via chains comprising:

first conductive segments formed at a first layer and second conductive segments formed at a second layer, said first conductive segments and said second conductive segments being interconnected by vias and forming geometrically shaped sections of said first via chains and said second via chains.

18. The structure according to claim 17, said geometrically shaped sections comprising one of:

geometric structures that alternate by type, across two or more layers of said wafer; and

serpentine and comb structures that alternate in type or instance, in a single layer of said wafer.

19. The structure according to claim 14, at least one of said first conductor and said second conductor comprising an electrically conductive spine having electrical connectors protruding from a base of said electrically conductive spine.

20. The structure according to claim 14, said first via chains alternating with said second via chains.