SEMICONDUCTOR PACKAGE HAVING A DISSIPATING PLATE

• US 20150221625A1
• Filed: 10/09/2014
• Published: 08/06/2015
• Est. Priority Date: 02/04/2014
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Min Kim
• Inventors: CHUN, HYUN-SUK, KIM, MIN
• Application Number:
  US14/510,571
• Publication Number:
  US 20150221625A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/17517 including bump connectors providing primarily mechanical support
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor package includes an integrated circuit device on a circuit board, a mold layer covering the integrated circuit board, a dissipating plate that dissipates heat from the integrated circuit device and a thermal conductive adhesive having a thermal interface material (TIM). The dissipating plate includes at least one protrusion protruding from a peripheral portion of the bottom of the dissipating plate that is inserted into the mold layer around the integrated circuit device. The dissipating plate is primarily secured to the mold layer by the protrusion, not by the thermal conductive adhesive. The thermal conductive adhesive includes a low modulus TIM (LMTIM) that supplementally adheres the dissipating plate to the mold layer.

Claims

1. A semiconductor package comprising:

a mold layer that secures an integrated circuit device to a circuit board and that encapsulates the integrated circuit device from its surroundings wherein the integrated circuit device is coplanar with an upper surface of the mold layer and an upper surface of the integrated circuit device is exposed through the mold layer;

a dissipating plate disposed on the integrated circuit device and the mold layer that is configured to dissipate heat from the integrated circuit device, the dissipating plate including at least one protrusion that protrudes from a peripheral portion of a bottom thereof and penetrates into the mold layer; and

a dissipating adhesive configured to adhere the dissipating plate to the mold layer and the integrated circuit device therebetween, the dissipating adhesive configured to transfer heat from the integrated circuit device to the dissipating plate.

2. The semiconductor package of claim 1, wherein the mold layer fills a gap space between the circuit board and the integrated circuit device and side spaces adjacent to the integrated circuit device.

3. The semiconductor package of claim 1, wherein the mold layer includes an under-fill mold in a gap space between the integrated circuit device and the circuit board and an encapsulant that fills side spaces adjacent to the integrated circuit device.

4. The semiconductor package of claim 1, wherein the dissipating plate makes contact with the upper surface of the mold layer and the upper surface of the integrated circuit device, and the mold layer includes at least one recess in the upper surface thereof that corresponds to the protrusion of the dissipating plate.

5. The semiconductor package of claim 4, wherein the protrusion and the recess are continuous along the peripheral portion of the bottom of the dissipating plate, wherein the protrusion has a ring shape that encloses the integrated circuit device in the mold layer.

6. The semiconductor package of claim 4, wherein the protrusion and the recess are discontinuous along the peripheral portion of the bottom of the dissipation plate, wherein the protrusion includes a plurality of protrusion pieces that are symmetric with each other with respect to the integrated circuit device.

7. The semiconductor package of claim 4, further comprising an additional adhesive between the protrusion and an inner surface of the recess.

8. The semiconductor package of claim 1, wherein the dissipating adhesive includes a penetration hole through which the protrusion penetrates and comprises a low modulus thermal interface material (LMTIM).

9. The semiconductor package of claim 1, further comprising:

an additional circuit board under the circuit board;

an additional integrated circuit device on the additional circuit board; and

at least one inter-board connector that connects the circuit board and the additional circuit board, wherein the semiconductor package has a package-on-package (PoP) structure.

10. The semiconductor package of claim 9, wherein the additional integrated circuit device includes a logic chip, and the integrated circuit device includes a plurality of stacked memory chips.

11. The semiconductor package of claim 10, wherein the integrated circuit device and the additional integrated circuit device include a flip chip structure, and the stacked memory chips are connected with each other by a plurality of inter-chip connectors.

12. The semiconductor package of claim 9, wherein the integrated circuit device and the additional integrated circuit device include a plurality of stacked memory chips.

13. A semiconductor package comprising:

a mold layer that secures an integrated circuit device to a circuit board and encapsulates the integrated circuit device from its surroundings and that includes at least one recess in a peripheral portion of an upper surface thereof;

a dissipating plate disposed on an upper surface of the integrated circuit device and an upper surface of the mold layer that is configured to dissipate heat from the integrated circuit device, the dissipating plate including at least one protrusion that protrudes from a peripheral portion of a bottom thereof and penetrates into the recess of the mold layer to combine with the mold layer with an interference fit; and

a dissipating adhesive between the dissipating plate and the mold layer and the integrated circuit device that includes a penetration hole through which the protrusion penetrates and comprises a low modulus thermal interface material (LMTIM) that is configured to transfer heat from the integrated circuit device to the dissipating plate.

14. The semiconductor package of claim 13, wherein an upper surface of the integrated circuit device is coplanar with an upper surface of the mold layer, and an upper surface of the integrated circuit device is exposed through the mold layer, and wherein the mold layer fills a gap space between the circuit board and the integrated circuit device and side spaces adjacent to the integrated circuit device.

15. The semiconductor package of claim 13, wherein an upper surface of the integrated circuit device is coplanar with an upper surface of the mold layer, the mold layer includes an under-fill mold in a gap space between the integrated circuit device and the circuit board and an encapsulant that fills side spaces adjacent to the integrated circuit device, and wherein an upper surface of the integrated circuit device is exposed through the encapsulant.

16. The semiconductor package of claim 13, wherein the protrusion and the recess are continuous along the peripheral portion of the bottom of the dissipating plate, wherein the protrusion has a ring shape that encloses the integrated circuit device in the mold layer.

17. The semiconductor package of claim 13, wherein the protrusion and the recess are discontinuous along the peripheral portion of the bottom of the dissipation plate, wherein the protrusion includes a plurality of protrusion pieces that are symmetric with each other with respect to the integrated circuit device.

18. The semiconductor package of claim 13, further comprising an additional adhesive between the protrusion and an inner surface of the recess.

19. The semiconductor package of claim 13, further comprising:

an additional circuit board under the circuit board;

an additional integrated circuit device on the additional circuit board; and

at least one inter-board connector that connects the circuit board and the additional circuit board, wherein the semiconductor package has a package-on-package (PoP) structure.

20. The semiconductor package of claim 19, wherein the integrated circuit device includes a plurality of stacked memory chips, the integrated circuit device and the additional integrated circuit device include a flip chip structure, and the stacked memory chips are connected with each other by a plurality of inter-chip connectors.