Thin FilmTransistor, Array Substrate, And Manufacturing Method Thereof

• US 20150221669A1
• Filed: 12/10/2012
• Published: 08/06/2015
• Est. Priority Date: 06/08/2012
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Sun, Shuang
• Application Number:
  US13/995,105
• Publication Number:
  US 20150221669A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor, an array substrate (1) and a manufacturing method thereof are provided. The thin film transistor comprises a substrate (1) and a gate electrode (2), a gate insulating layer (3), a semiconductor layer (4), a protective layer (5), an ohmic contact layer (6), a source electrode (7) and a drain electrode (8) successively stacked on the substrate (1), wherein the protective layer (5) has two via holes (11) over the semiconductor layer (4) so as to expose the underlying semiconductor layer (4), the semiconductor layer (4) exposed by the via hole (11) is covered by the ohmic contact layer (6); the source and drain electrodes (7, 8) are connected to the semiconductor layer (4) through the ohmic contact layer (6) at the via hole (11).

Claims

1. A thin film transistor, comprising a substrate and a gate electrode, a gate insulating layer, a semiconductor layer, a protective layer, an ohmic contact layer, a source electrode and a drain electrode successively stacked on the substrate, wherein the protective layer has two via holes over the semiconductor layer so as to expose the underlying semiconductor layer, the semiconductor layer exposed by the via hole is covered by the ohmic contact layer;

the source and drain electrodes are connected to the semiconductor layer through the ohmic contact layer at the via hole.

2. The thin film transistor according to claim 1, wherein the gate electrode, the gate insulating layer and the semiconductor layer are of a same shape.

3. The thin film transistor according to claim 1, wherein the source electrode and the drain electrode have a same shape as that of the ohmic contact layer.

4. The thin film transistor according to claim 1, wherein the ohmic contact layer is formed by a doped semiconductor film.

5. The thin film transistor according to claim 1, wherein the semiconductor layer has a thickness of 400′

to 1500′

.

6. An array substrate, comprising the thin film transistor according to claim 1, wherein it further comprises a passivation layer, a pixel electrode, a gate line and a data line, the pixel electrode is connected to the drain electrode, the gate line is connected to the gate electrode, and the data line is connected to the source electrode.

7. The array substrate according to claim 6, wherein the passivation layer overlays the thin film transistor, the pixel electrode is located in a region not covered by the passivation layer.

8. A manufacturing method of an array substrate, comprising the steps of:

S1, forming patterns including a gate line, a gate electrode, a gate insulating layer and a semiconductor layer on a substrate;

S2, forming a pattern of a protective layer, the protective layer having two via holes formed therein at locations opposed to the semiconductor layer so as to expose the semiconductor layer;

S3, forming patterns including an ohmic contact layer, a data line, a source electrode, and a drain electrode, wherein the ohmic contact layer is formed on at least the semiconductor layer exposed by the via holes, the source and drain electrodes are connected to the semiconductor layer through the ohmic contact layer at the via holes;

S4, forming a pattern of a passivation layer, wherein the passivation layer has a gate line interface via hole and a data line interface via hole provided therein; and

S5, forming a pattern of a pixel electrode.

9. The manufacturing method of the array substrate according to claim 8, wherein the step S1 comprises:

S101, forming a gate metal film, a gate insulating layer film and a semiconductor film successively on the substrate;

S102, forming photoresist on the semiconductor film;

S103, exposing and developing by using a gray mask or a half-tone mask, so that the photoresist in a region of a gate electrode is completely retained, the photoresist in a region of a gate line is partially retained, and remaining portion of the photoresist is completely removed; and

S104, forming patterns including the gate line, the gate electrode, a gate insulating layer and a semiconductor layer through multi-step etching, and removing the remaining photoresist.

10. The manufacturing method of the array substrate according to claim 8, wherein the step S2 comprises:

S201, forming a protective layer film on the substrate after the step S1;

S202, forming photoresist on the protective layer film;

S203, exposing and developing by using a normal masking process, so that the photoresist at via holes to be formed in the protective layer film is completely removed, remaining portion of the photoresist is completely retained; and

S204, etching off the protective layer film in the region where the photoresist is completely removed by a dry etch method, so as to form protective layer via holes, and removing the remaining photoresist.

11. The manufacturing method of the array substrate according to claim 8, wherein the step S3 comprises:

S301, forming a doped semiconductor film and a source-drain metal film continuously on the substrate after the step S2;

S302, forming photoresist on the source-drain metal film;

S303, exposing and developing by using a normal masking process, so that the photoresist in a region including a data line, a source electrode and a drain electrode is completely retained, and remaining portion of the photoresist is completely removed; and

S304, etching off the source-drain metal film and the doped semiconductor film in the region where the photoresist is completely removed by a dry etch method so as to form patterns including an ohmic contact layer, the data line, the source electrode, and the drain electrode, and removing the remaining photoresist.

12. The manufacturing method of the array substrate according to claim 8, wherein the step S4 comprises:

S401, forming a passivation layer film on the substrate after the step S3;

S402, forming photoresist on the passivation layer film;

S403, exposing and developing by using a normal masking process, so that the photoresist in a region including a gate line interface via hole, a data line interface via hole and a pixel electrode is completely removed, and remaining portion of the photoresist is completely retained; and

S404, etching off the passivation layer film in the region where the photoresist is completely removed by a dry etch method so as to from a pattern of a passivation layer, the gate line interface via hole and a data line interface via hole being provided in the passivation layer.

13. The manufacturing method of the array substrate according to claim 8, wherein the step S5 comprises:

forming a transparent conductive film on the substrate after the step S404, lifting off the photoresist so that the transparent conductive film thereon is removed together, so as to form a pattern of a pixel electrode.