FinFET DEVICE CONTAINING A COMPOSITE SPACER STRUCTURE

• US 20150221676A1
• Filed: 02/04/2014
• Published: 08/06/2015
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Holt, Judson R., Li, Jinghong, Mehta, Sanjay, Reznicek, Alexander, Schepis, Dominic J.
• Granted Patent: US 9,236,397 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02329 introduction of nitrogen
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A composite spacer structure is formed on vertical sidewalls of a gate structure that is formed straddling a semiconductor fin. In one embodiment, the composite spacer structure includes an inner low-k dielectric material portion and an outer nitride material portion.

Claims

1. A method of forming a FinFET device comprising:

providing a plurality of semiconductor fins on a surface of a substrate;

forming at least one gate structure orientated perpendicular to and straddling each semiconductor fin of the plurality of semiconductor fins;

providing a composite spacer structure on vertical sidewalls of each gate structure, wherein said composite spacer structure comprises an inner low-k dielectric material portion and an outer nitride material portion; and

epitaxially growing a source-side doped semiconductor material portion on an exposed surface of each semiconductor fin and on one side of each gate structure and a drain-side doped semiconductor portion on another exposed surface of each semiconductor fin and on another side of each gate structure.

2. The method of claim 1, wherein said providing said plurality of semiconductor fins comprises lithography and etching of a semiconductor material layer of a semiconductor-on-insulator substrate or an upper semiconductor portion of a bulk semiconductor substrate.

3. The method of claim 1, wherein said at least one gate structure is a functional gate structure comprising a gate dielectric portion and a gate conductor portion.

4. The method of claim 1, wherein said at least one gate structure is a sacrificial gate structure and wherein said sacrificial gate structure is replaced with a functional gate structure after said epitaxially growing said source-side doped semiconductor material portion and said drain-side doped semiconductor portion.

5. The method of claim 1, wherein said providing said composite spacer structure comprises forming a dielectric spacer comprising a low-k dielectric material and converting an outer surface of the dielectric spacer into said outer nitride material portion.

6. The method of claim 5, wherein said converting is selected from the group consisting of decoupled plasma nitridation, plasma treatment, a rapid thermal anneal in a nitrogen-containing ambient, and ion implantation of nitrogen.

7. The method of claim 1, wherein said providing said composite spacer structure comprises depositing a graded spacer profile.

8. The method of claim 1, further comprising forming a source-side metal semiconductor alloy portion located on a surface of said source-side doped semiconductor material portion and a drain-side metal semiconductor alloy portion located on a surface of said drain-side doped semiconductor material portion.

9. The method of claim 8, further comprising forming a dielectric material having at least one contact structure located therein.

10. The method of claim 1, wherein said inner low-k dielectric material portion of said composite spacer structure is selected from the group consisting of SiOCN, SiCBN, SiCOH, SiCN and SiON.

11. A FinFET device comprising:

a plurality of semiconductor fins located on a surface of a substrate;

at least one gate structure orientated perpendicular to and straddling each semiconductor fin of the plurality of semiconductor fins;

a composite spacer structure located on vertical sidewalls of each gate structure, wherein said composite spacer structure comprises an inner low-k dielectric material portion and an outer nitride material portion;

a source-side doped semiconductor material portion on an exposed surface of each semiconductor fin and on one side of each gate structure; and

a drain-side doped semiconductor portion on another exposed surface of each semiconductor fin and on another side of each gate structure.

12. The FinFET device of claim 11, further comprising a source-side metal semiconductor alloy portion located on a surface of said source-side doped semiconductor material portion and a drain-side metal semiconductor alloy portion located on a surface of said drain-side doped semiconductor material portion.

13. The FinFET device of claim 12, further comprising a dielectric material located atop at least said substrate and said plurality of semiconductor fins, wherein said dielectric material includes at least one contact structure located therein.

14. The FinFET device of claim 11, wherein said substrate is an insulator layer of a semiconductor-on-insulator substrate.

15. The FinFET device of claim 11, wherein said substrate is a semiconductor portion of a bulk semiconductor substrate.

16. The FinFET device of claim 11, wherein said inner low-k dielectric material portion of said composite spacer structure is selected from the group consisting of SiOCN, SiCBN, SiCOH, SiCN and SiON.

17. The FinFET device of claim 11, wherein each semiconductor fin of said plurality of semiconductor fins comprises single crystalline silicon.

18. The FinFET device of claim 11, wherein said gate structure is a functional gate structure comprising a gate dielectric portion and a gate conductor portion.

19. The FinFET device of claim 11, wherein said source-side doped semiconductor material portion, said drain-side doped semiconductor portion, and each of said semiconductor fins of said plurality of semiconductor fins comprises a same semiconductor material.

20. A FinFET device comprising:

a plurality of semiconductor fins located on a surface of a substrate;

at least one gate structure orientated perpendicular to and straddling each semiconductor fin of the plurality of semiconductor fins;

a composite spacer structure located on vertical sidewalls of each gate structure, wherein said composite spacer structure comprises an inner low-k dielectric material portion and an outer doped material portion;

a source-side doped semiconductor material portion on an exposed surface of each semiconductor fin and on one side of each gate structure; and

a drain-side doped semiconductor portion on another exposed surface of each semiconductor fin and on another side of each gate structure.