LAYERED STRUCTURE, THIN FILM TRANSISTOR ARRAY, AND METHOD OF MANUFACTURING THE SAME
First Claim
1. A layered structure comprising:
- a first electrode layer on an insulating substrate;
a first insulating film on the first electrode layer;
a second electrode layer on the first insulating film;
a second insulating film on the second electrode layer; and
a third electrode layer on the second insulating film,wherein the first electrode layer, an opening of the first insulating film, the second electrode layer, an opening of the second insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected,the third electrode layer relaying or reinforcing, through the opening of the second insulating film, a connection between the first electrode layer and the second electrode layer.
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Abstract
A layered structure includes a first electrode layer on an insulating substrate, a first insulating film on the first electrode layer, a second electrode layer on the first insulating film, a second insulating film on the second electrode layer, and a third electrode layer on the second insulating film. The first electrode layer, an opening of the first insulating film, the second electrode layer, an opening of the second insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected. The third electrode layer relays or reinforces, through the opening of the second insulating film, a connection between the first electrode layer and the second electrode layer formed on the first insulating film.
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Citations
21 Claims
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1. A layered structure comprising:
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a first electrode layer on an insulating substrate; a first insulating film on the first electrode layer; a second electrode layer on the first insulating film; a second insulating film on the second electrode layer; and a third electrode layer on the second insulating film, wherein the first electrode layer, an opening of the first insulating film, the second electrode layer, an opening of the second insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected, the third electrode layer relaying or reinforcing, through the opening of the second insulating film, a connection between the first electrode layer and the second electrode layer.
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2. A thin film transistor array comprising, on an insulating substrate:
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a first electrode layer including; a gate wire; a gate electrode connected to the gate wire; a capacitor wire; and a capacitor electrode connected to the capacitor wire; a gate insulating film on the first electrode layer; a second electrode layer on the gate insulating film, the second electrode layer including; a source wire; a source electrode connected to the source wire; a drain electrode; and a pixel electrode connected to the drain electrode; a semiconductor located between the source electrode and the drain electrode, the gate electrode overlapping the semiconductor via the gate insulating film, the capacitor electrode overlapping the pixel electrode via the gate insulating film; an interlayer insulating film having an opening on the pixel electrode; and a third electrode layer including an upper pixel electrode connected to the pixel electrode via the opening, wherein the first electrode layer, an opening of the gate insulating film, the second electrode layer, the opening of the interlayer insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected, the third electrode layer relaying or reinforcing, through the opening of the interlayer insulating film, a connection between the first electrode layer and the second electrode layer formed on the gate insulating film. - View Dependent Claims (3, 4, 5)
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6. A thin film transistor array comprising, on an insulating substrate:
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a first electrode layer including; a source wire; a source electrode connected to the source wire; a drain electrode; and a pixel electrode connected to the drain electrode; semiconductors between the source electrodes and the drain electrodes; a gate insulating film having an opening on the pixel electrode; a second electrode layer on the gate insulating film, the second electrode layer including; a gate wire; a gate electrode connected to the gate wire; a capacitor wire; and a capacitor electrode connected to the capacitor wire, the gate electrode overlapping the semiconductor via the gate insulating film, the capacitor electrode overlapping the pixel electrode via the gate insulating film; an interlayer insulating film having an opening above the opening of the gate insulating film; and a third electrode layer including an upper pixel electrode connected to the pixel electrode via the opening of the interlayer insulating film, wherein the first electrode layer, the opening of the gate insulating film, the second electrode layer, the opening of the interlayer insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected, the third electrode layer relaying or reinforcing, through the opening of the interlayer insulating film, a connection between the first electrode layer and the second electrode layer formed on the gate insulating film. - View Dependent Claims (7, 8, 9)
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10. A method of manufacturing a layered structure, the method comprising the steps of:
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forming a first electrode layer on an insulating substrate; depositing a first insulating film having an opening such that at least a portion of the first electrode layer is included in the opening; forming a second electrode layer such that the second electrode layer overlaps or adjoins at least a portion of the opening of the first insulating film; depositing a second insulating film having an opening such that the opening covers at least the portion of the first electrode layer included in the opening of the first insulating film, and includes a portion of the second electrode layer; and forming a third electrode layer such that the third electrode layer relays or reinforces, at least through the opening of the interlayer insulating film, a connection between the portion of the first electrode layer in the opening of the first insulating film and the portion of the second electrode layer on the first insulating film, wherein the step of forming the second electrode layer forms the second electrode layer using printing. - View Dependent Claims (17, 18)
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11. A method of manufacturing a thin film transistor array, the method comprising the steps of:
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forming a first electrode layer on an insulating substrate, the first electrode layer including; a gate wire; a gate electrode connected to the gate wire; a capacitor wire; a capacitor electrode connected to the capacitor wire; gates of a gate protective element and a source protective element; and a source connection electrode; depositing, on the substrate on which the first electrode layer has been formed, a gate insulating film having openings to the gates of the gate protective element and source protective element and to the source common electrode; forming, on the substrate on which the gate insulating film has been deposited, a second electrode layer, the second electrode layer including; a source wire; a source electrode connected to the source wire; a drain electrode; a pixel electrode connected to the drain electrode; sources and drains of the gate protective element and the source protective element; and a gate common electrode; forming a semiconductor between the source electrode and the drain electrode; depositing an interlayer insulating film having openings located above the pixel electrode and the openings of the gate insulating film; and forming a third electrode layer, the third electrode layer including; an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film on the pixel electrode; a first connection reinforcement electrode on a stack structure of; the gate of the gate protective element, a corresponding one of the openings of the gate insulating film, the drain of the gate protective element, and a corresponding one of the openings of the interlayer insulating film in this order, a second connection reinforcement electrode on a stack structure of; the gate wire, a corresponding one of the openings of the gate insulating film, the source or drain of the gate or source protective element, and a corresponding one of the openings of the interlayer insulating film in this order, a third connection reinforcement electrode on a stack structure of; the gate of the source protective element, a corresponding one of the openings of the gate insulating film, the drain of the source protective element, and a corresponding one of the openings of the interlayer insulating film in this order, and a fourth connection reinforcement electrode having a stack structure of; the source common electrode, a corresponding one of the openings of the gate insulating film, the source or drain of the source protective element, and a corresponding one of the openings of the interlayer insulating film in this order, wherein the step of forming the second electrode layer forms the second electrode layer using printing. - View Dependent Claims (19, 20, 21)
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12. A method of manufacturing a thin film transistor array, the method comprising the steps of:
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forming a first electrode layer on an insulating substrate, the first electrode layer including; a gate connection electrode; a gate wire; a gate electrode connected to the gate wire; a capacitor wire; a capacitor electrode connected to the capacitor wire; and a source connection electrode; depositing a gate insulating film having an opening to the source connection electrode; forming, on the substrate on which the gate insulating film has been deposited, a second electrode layer, the second electrode layer including; a source wire; a source electrode connected to the source wire; a drain electrode; and a pixel electrode connected to the drain electrode; forming a semiconductor between the source electrode and the drain electrode; depositing an interlayer insulating film having openings located above the pixel electrode and the opening of the gate insulating film; and forming a third electrode layer, the third electrode layer including; an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film located above the pixel electrode; and a connection reinforcement electrode on a stack structure of; the source connection electrode, the opening of the gate insulating film, the source wire, and a corresponding one of the openings of the interlayer insulating film in this order, wherein the step of forming the second electrode layer forms the second electrode layer using printing.
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13. A method of manufacturing a thin film transistor array, the method comprising the steps of:
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forming a first electrode layer on an insulating substrate, the first electrode layer including; a gate wire; a gate electrode connected to the gate wire; a capacitor wire; and a capacitor electrode connected to the capacitor wire; depositing a gate insulating film having an opening on the gate wire; forming, on the substrate on which the gate insulating film has been deposited, a second electrode layer, the second electrode layer including; a source connection electrode; a source wire; a source electrode connected to the source wire; a drain electrode; a pixel electrode connected to the drain electrode; and a gate connection electrode; forming a semiconductor between the source electrode and the drain electrode; depositing an interlayer insulating film having openings located above the pixel electrode and the opening of the gate insulating film; and forming a third electrode layer, the third electrode layer including; an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film located above the pixel electrode; and a connection reinforcement electrode on a stack structure of; the gate wire; the opening of the gate insulating film, the gate connection electrode; and a corresponding one of the openings of the interlayer insulating film in this order, wherein the step of forming the second electrode layer forms the second electrode layer using printing.
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14. A method of manufacturing a thin film transistor array, the method comprising the steps of:
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forming a first electrode layer on an insulating substrate, the first electrode layer including; a source wire; a source electrode connected to the source wire; a drain electrode; a pixel electrode connected to the drain electrode; drains and sources of a gate protective element and a source protective element; and a gate common electrode; forming a semiconductor between the source electrode and the drain electrode; depositing, on the substrate on which the first electrode layer and the semiconductor have been formed, a gate insulating film having openings to the drains of the gate protective element and source protective element and to the gate common electrode; forming, on the substrate on which the gate insulating film has been deposited, a second electrode layer, the second electrode layer including; a gate wire; a gate electrode connected to the gate wire; a capacitor wire; a capacitor electrode connected to the capacitor wire; gates of the gate protective element and source protective element; and a source common electrode; depositing an interlayer insulating film having openings located above the pixel electrode and the openings of the gate insulating film; and forming a third electrode layer, the third electrode layer including; an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film located above the pixel electrode; a first connection reinforcement electrode having a stack structure of; the drain of the gate protective element, a corresponding one of the openings of the gate insulating film, the gate of the gate protective element, and a corresponding one of the openings of the interlayer insulating film in this order, a second connection reinforcement electrode having a stack structure of; the source and drain of the gate protective element, a corresponding one of the openings of the gate insulating film, the gate common electrode, and a corresponding one of the openings of the interlayer insulating film in this order, a third connection reinforcement electrode having a stack structure of; the drain of the source protective element, a corresponding one of the openings of the gate insulating film, the gate of the source protective element, and a corresponding one of the openings of the interlayer insulating film in this order, and a fourth connection reinforcement electrode having a stack structure of; the source or drain of the source protective element, a corresponding one of the openings of the gate insulating film, the source common electrode, and a corresponding one of the openings of the interlayer insulating film in this order, wherein the step of forming the second electrode layer forms the second electrode layer using printing.
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15. A method of manufacturing a thin film transistor array, the method comprising the steps of:
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forming a first electrode layer on an insulating substrate, the first electrode layer including; a source connection electrode; a source wire; a source electrode connected to the source wire; a drain electrode; a pixel electrode connected to the drain electrode; and a gate connection electrode; depositing a gate insulating film having an opening to the gate connection electrode; forming, on the substrate on which the gate insulating film has been deposited, a second electrode layer, the second electrode layer including; a gate wire; a gate electrode connected to the source wire; a capacitor wire; and a capacitor electrode connected to the capacitor wire; forming a semiconductor between the source electrode and the drain electrode; depositing, on the substrate on which the first electrode layer and the semiconductor have been formed, an interlayer insulating film having openings located above the pixel electrode and the opening of the gate insulating film; and forming a third electrode layer, the third electrode layer including; an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film located above the pixel electrode; and a connection reinforcement electrode having a stack structure of; the gate connection electrode, the opening of the gate insulating film, the gate wire, and a corresponding one of the openings of the interlayer insulating film in this order, wherein the step of forming the second electrode layer forms the second electrode layer using printing.
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16. A method of manufacturing a thin film transistor array, the method comprising the steps of:
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forming a first electrode layer on an insulating substrate, the first electrode layer including; a source wire; a source electrode connected to the source wire; a drain electrode; and a pixel electrode connected to the drain electrode; forming a semiconductor between the source electrode and the drain electrode; depositing a gate insulating film having an opening to the source wire; forming, on the substrate on which the gate insulating film has been deposited, a second electrode layer, the second electrode layer including; a gate connection electrode; a gate wire; a gate electrode connected to the source wire; a capacitor wire; a capacitor electrode connected to the capacitor wire; and a source connection electrode; depositing an interlayer insulating film having openings located above the pixel electrode and the opening of the gate insulating film; and forming a third electrode layer, the third electrode layer including; an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film located above the pixel electrode; and a connection reinforcement electrode having a stack structure of; the source wire, the opening of the gate insulating film, the source connection electrode, and a corresponding one of the openings of the interlayer insulating film in this order, wherein the step of forming the second electrode layer forms the second electrode layer using printing.
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Specification