LAYERED STRUCTURE, THIN FILM TRANSISTOR ARRAY, AND METHOD OF MANUFACTURING THE SAME

• US 20150221685A1
• Filed: 03/20/2015
• Published: 08/06/2015
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Toppan Printing Co., Ltd. (TOPPAN Holdings, Inc.)
• Original Assignee: Toppan Printing Co., Ltd. (TOPPAN Holdings, Inc.)
• Inventors: Hatta, Kaoru, ISHIZAKI, Mamoru
• Granted Patent: US 9,530,809 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence

Abstract

A layered structure includes a first electrode layer on an insulating substrate, a first insulating film on the first electrode layer, a second electrode layer on the first insulating film, a second insulating film on the second electrode layer, and a third electrode layer on the second insulating film. The first electrode layer, an opening of the first insulating film, the second electrode layer, an opening of the second insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected. The third electrode layer relays or reinforces, through the opening of the second insulating film, a connection between the first electrode layer and the second electrode layer formed on the first insulating film.

Claims

1. A layered structure comprising:

a first electrode layer on an insulating substrate;

a first insulating film on the first electrode layer;

a second electrode layer on the first insulating film;

a second insulating film on the second electrode layer; and

a third electrode layer on the second insulating film,

wherein the first electrode layer, an opening of the first insulating film, the second electrode layer, an opening of the second insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected,

the third electrode layer relaying or reinforcing, through the opening of the second insulating film, a connection between the first electrode layer and the second electrode layer.

2. A thin film transistor array comprising, on an insulating substrate:

a first electrode layer including;

a gate wire;

a gate electrode connected to the gate wire;

a capacitor wire; and

a capacitor electrode connected to the capacitor wire;

a gate insulating film on the first electrode layer;

a second electrode layer on the gate insulating film, the second electrode layer including;

a source wire;

a source electrode connected to the source wire;

a drain electrode; and

a pixel electrode connected to the drain electrode;

a semiconductor located between the source electrode and the drain electrode, the gate electrode overlapping the semiconductor via the gate insulating film, the capacitor electrode overlapping the pixel electrode via the gate insulating film;

an interlayer insulating film having an opening on the pixel electrode; and

a third electrode layer including an upper pixel electrode connected to the pixel electrode via the opening,

wherein the first electrode layer, an opening of the gate insulating film, the second electrode layer, the opening of the interlayer insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected,

the third electrode layer relaying or reinforcing, through the opening of the interlayer insulating film, a connection between the first electrode layer and the second electrode layer formed on the gate insulating film.

3. The thin film transistor array according to claim 2, further comprising:

a common electrode around the thin film transistor array, the common electrode comprising a gate common electrode and a source common electrode;

gate protective elements located between the gate wires and the gate common electrode;

source protective elements located between the source wires and the source common electrode, the common electrode being directly connected to a ground potential or the ground potential via a resistor,

wherein;

the gate common electrode is included in the second electrode layer,

the source common electrode is included in the first electrode layer,

at least one of the gate protective element and the source protective element comprises;

a pair of diode-connected thin film transistors connected in parallel to each other such that one of the diode-connected thin film transistors is opposite in direction to the other thereof;

a pair of diode-connected thin film transistors connected in series to each other such that one of the diode-connected thin film transistors is opposite in direction to the other thereof;

or

a floating-gate thin film transistor, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, at least one of;

a short-circuit portion between a gate electrode and a source electrode of the gate protective element;

a short-circuit portion between a gate electrode and a source electrode of the source protective element;

a connection portion between the gate wire and the gate protective element; and

a connection portion between the source protective element and the source common electrode.

4. The thin film transistor array according to claim 2, wherein:

the gate connection electrode and the source connection electrode of the thin film transistor array are included in the first electrode layer, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, a connection portion between the source connection electrode and the source wire.

5. The thin film transistor array according to claim 2, wherein:

the gate connection electrode and the source connection electrode of the thin film transistor array are included in the second electrode layer, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, a connection portion between the gate wire and the gate connection electrode.

6. A thin film transistor array comprising, on an insulating substrate:

a first electrode layer including;

a source wire;

a source electrode connected to the source wire;

a drain electrode; and

a pixel electrode connected to the drain electrode;

semiconductors between the source electrodes and the drain electrodes;

a gate insulating film having an opening on the pixel electrode;

a second electrode layer on the gate insulating film, the second electrode layer including;

a gate wire;

a gate electrode connected to the gate wire;

a capacitor wire; and

a capacitor electrode connected to the capacitor wire,

the gate electrode overlapping the semiconductor via the gate insulating film, the capacitor electrode overlapping the pixel electrode via the gate insulating film;

an interlayer insulating film having an opening above the opening of the gate insulating film; and

a third electrode layer including an upper pixel electrode connected to the pixel electrode via the opening of the interlayer insulating film,

wherein the first electrode layer, the opening of the gate insulating film, the second electrode layer, the opening of the interlayer insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected,

the third electrode layer relaying or reinforcing, through the opening of the interlayer insulating film, a connection between the first electrode layer and the second electrode layer formed on the gate insulating film.

7. The thin film transistor array according to claim 6, further comprising:

a common electrode around the thin film transistor array, the common electrode comprising a gate common electrode and a source common electrode;

a gate protective element located between the gate wire and the gate common electrode;

a source protective element located between the source wire and the source common electrode, the common electrode being directly connected to a ground potential or the ground potential via a resistor,

wherein;

the gate common electrode is included in the first electrode layer,

the source common electrode is included in the second electrode layer,

at least one of the gate protective element and the source protective element comprises;

a pair of diode-connected thin film transistors connected in parallel to each other such that one of the diode-connected thin film transistors is opposite in direction to the other thereof;

a pair of diode-connected thin film transistors connected in series to each other such that one of the diode-connected thin film transistors is opposite in direction to the other thereof;

or

a floating-gate thin film transistor, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, at least one of;

a short-circuit portion between a drain electrode and a gate electrode of the gate protective element;

a short-circuit portion between a drain electrode and a gate electrode of the source protective element;

a connection portion between the gate protective element and the gate wire; and

a connection portion between the source common electrode and the source protective element.

8. The thin film transistor array according to claim 6, wherein:

the gate connection electrode and the source connection electrode of the thin film transistor array are included in the first electrode layer, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, a connection portion between the gate connection electrode and the gate wire.

9. The thin film transistor array according to claim 6, wherein:

the gate connection electrode and the source connection electrode of the thin film transistor array are included in the second electrode layer, and

the third electrode layer relays or reinforces, as the connection between the first electrode layer and the second electrode layer, a connection portion between the source wire and the source connection electrode.

10. A method of manufacturing a layered structure, the method comprising the steps of:

forming a first electrode layer on an insulating substrate;

depositing a first insulating film having an opening such that at least a portion of the first electrode layer is included in the opening;

forming a second electrode layer such that the second electrode layer overlaps or adjoins at least a portion of the opening of the first insulating film;

depositing a second insulating film having an opening such that the opening covers at least the portion of the first electrode layer included in the opening of the first insulating film, and includes a portion of the second electrode layer; and

forming a third electrode layer such that the third electrode layer relays or reinforces, at least through the opening of the interlayer insulating film, a connection between the portion of the first electrode layer in the opening of the first insulating film and the portion of the second electrode layer on the first insulating film,

wherein the step of forming the second electrode layer forms the second electrode layer using printing.

17. The method of manufacturing a layered structure according to claim 10, wherein at least the step of forming the second electrode layer forms the second electrode layer using reverse-offset printing.

18. The method of manufacturing a layered structure according to claim 10, wherein at least the step of forming the third electrode layer forms the third electrode layer using screen printing or gravure-offset printing.

11. A method of manufacturing a thin film transistor array, the method comprising the steps of:

forming a first electrode layer on an insulating substrate, the first electrode layer including;

a gate wire;

a gate electrode connected to the gate wire;

a capacitor wire;

a capacitor electrode connected to the capacitor wire;

gates of a gate protective element and a source protective element; and

a source connection electrode;

depositing, on the substrate on which the first electrode layer has been formed, a gate insulating film having openings to the gates of the gate protective element and source protective element and to the source common electrode;

forming, on the substrate on which the gate insulating film has been deposited, a second electrode layer, the second electrode layer including;

a source wire;

a source electrode connected to the source wire;

a drain electrode;

a pixel electrode connected to the drain electrode;

sources and drains of the gate protective element and the source protective element; and

a gate common electrode;

forming a semiconductor between the source electrode and the drain electrode;

depositing an interlayer insulating film having openings located above the pixel electrode and the openings of the gate insulating film; and

forming a third electrode layer, the third electrode layer including;

an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film on the pixel electrode;

a first connection reinforcement electrode on a stack structure of;

the gate of the gate protective element,

a corresponding one of the openings of the gate insulating film,

the drain of the gate protective element, and

a corresponding one of the openings of the interlayer insulating film in this order,

a second connection reinforcement electrode on a stack structure of;

the gate wire,

a corresponding one of the openings of the gate insulating film,

the source or drain of the gate or source protective element, and

a corresponding one of the openings of the interlayer insulating film in this order,

a third connection reinforcement electrode on a stack structure of;

the gate of the source protective element,

a corresponding one of the openings of the gate insulating film,

the drain of the source protective element, and

a corresponding one of the openings of the interlayer insulating film in this order, and

a fourth connection reinforcement electrode having a stack structure of;

the source common electrode,

a corresponding one of the openings of the gate insulating film,

the source or drain of the source protective element, and

a corresponding one of the openings of the interlayer insulating film in this order,

wherein the step of forming the second electrode layer forms the second electrode layer using printing.

19. The method of manufacturing a thin film transistor array according to claim 11, wherein at least the step of forming the second electrode layer forms the second electrode layer using reverse-offset printing.

20. The method of manufacturing a thin film transistor array according to claim 11, wherein at least the step of forming the third electrode layer forms the third electrode layer using screen printing or gravure-offset printing.

21. The method of manufacturing a thin film transistor array according to claim 19, wherein at least the step of forming the third electrode layer forms the third electrode layer using screen printing or gravure-offset printing.

12. A method of manufacturing a thin film transistor array, the method comprising the steps of:

forming a first electrode layer on an insulating substrate, the first electrode layer including;

a gate connection electrode;

a gate wire;

a gate electrode connected to the gate wire;

a capacitor wire;

a capacitor electrode connected to the capacitor wire; and

a source connection electrode;

depositing a gate insulating film having an opening to the source connection electrode;

forming, on the substrate on which the gate insulating film has been deposited,

a second electrode layer, the second electrode layer including;

a source wire;

a source electrode connected to the source wire;

a drain electrode; and

a pixel electrode connected to the drain electrode;

forming a semiconductor between the source electrode and the drain electrode;

depositing an interlayer insulating film having openings located above the pixel electrode and the opening of the gate insulating film; and

forming a third electrode layer,

the third electrode layer including;

an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film located above the pixel electrode; and

a connection reinforcement electrode on a stack structure of;

the source connection electrode,

the opening of the gate insulating film,

the source wire, and

a corresponding one of the openings of the interlayer insulating film in this order,

wherein the step of forming the second electrode layer forms the second electrode layer using printing.

13. A method of manufacturing a thin film transistor array, the method comprising the steps of:

forming a first electrode layer on an insulating substrate, the first electrode layer including;

a gate wire;

a gate electrode connected to the gate wire;

a capacitor wire; and

a capacitor electrode connected to the capacitor wire;

depositing a gate insulating film having an opening on the gate wire;

forming, on the substrate on which the gate insulating film has been deposited,

a second electrode layer, the second electrode layer including;

a source connection electrode;

a source wire;

a source electrode connected to the source wire;

a drain electrode;

a pixel electrode connected to the drain electrode; and

a gate connection electrode;

forming a semiconductor between the source electrode and the drain electrode;

depositing an interlayer insulating film having openings located above the pixel electrode and the opening of the gate insulating film; and

forming a third electrode layer, the third electrode layer including;

an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film located above the pixel electrode; and

a connection reinforcement electrode on a stack structure of;

the gate wire;

the opening of the gate insulating film, the gate connection electrode; and

a corresponding one of the openings of the interlayer insulating film in this order,

wherein the step of forming the second electrode layer forms the second electrode layer using printing.

14. A method of manufacturing a thin film transistor array, the method comprising the steps of:

forming a first electrode layer on an insulating substrate, the first electrode layer including;

a source wire;

a source electrode connected to the source wire;

a drain electrode;

a pixel electrode connected to the drain electrode;

drains and sources of a gate protective element and a source protective element; and

a gate common electrode;

forming a semiconductor between the source electrode and the drain electrode;

depositing, on the substrate on which the first electrode layer and the semiconductor have been formed, a gate insulating film having openings to the drains of the gate protective element and source protective element and to the gate common electrode;

forming, on the substrate on which the gate insulating film has been deposited, a second electrode layer, the second electrode layer including;

a gate wire;

a gate electrode connected to the gate wire;

a capacitor wire;

a capacitor electrode connected to the capacitor wire;

gates of the gate protective element and source protective element; and

a source common electrode;

depositing an interlayer insulating film having openings located above the pixel electrode and the openings of the gate insulating film; and

forming a third electrode layer,

the third electrode layer including;

an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film located above the pixel electrode;

a first connection reinforcement electrode having a stack structure of;

the drain of the gate protective element,

a corresponding one of the openings of the gate insulating film,

the gate of the gate protective element, and

a corresponding one of the openings of the interlayer insulating film in this order,

a second connection reinforcement electrode having a stack structure of;

the source and drain of the gate protective element,

a corresponding one of the openings of the gate insulating film,

the gate common electrode, and

a corresponding one of the openings of the interlayer insulating film in this order,

a third connection reinforcement electrode having a stack structure of;

the drain of the source protective element,

a corresponding one of the openings of the gate insulating film,

the gate of the source protective element, and

a corresponding one of the openings of the interlayer insulating film in this order, and

a fourth connection reinforcement electrode having a stack structure of;

the source or drain of the source protective element,

a corresponding one of the openings of the gate insulating film,

the source common electrode, and

a corresponding one of the openings of the interlayer insulating film in this order,

wherein the step of forming the second electrode layer forms the second electrode layer using printing.

15. A method of manufacturing a thin film transistor array, the method comprising the steps of:

forming a first electrode layer on an insulating substrate, the first electrode layer including;

a source connection electrode;

a source wire;

a source electrode connected to the source wire;

a drain electrode;

a pixel electrode connected to the drain electrode; and

a gate connection electrode;

depositing a gate insulating film having an opening to the gate connection electrode;

forming, on the substrate on which the gate insulating film has been deposited, a second electrode layer, the second electrode layer including;

a gate wire;

a gate electrode connected to the source wire;

a capacitor wire; and

a capacitor electrode connected to the capacitor wire;

forming a semiconductor between the source electrode and the drain electrode;

depositing, on the substrate on which the first electrode layer and the semiconductor have been formed, an interlayer insulating film having openings located above the pixel electrode and the opening of the gate insulating film; and

forming a third electrode layer,

the third electrode layer including;

an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film located above the pixel electrode; and

a connection reinforcement electrode having a stack structure of;

the gate connection electrode,

the opening of the gate insulating film,

the gate wire, and

a corresponding one of the openings of the interlayer insulating film in this order,

wherein the step of forming the second electrode layer forms the second electrode layer using printing.

16. A method of manufacturing a thin film transistor array, the method comprising the steps of:

forming a first electrode layer on an insulating substrate, the first electrode layer including;

a source wire;

a source electrode connected to the source wire;

a drain electrode; and

a pixel electrode connected to the drain electrode;

forming a semiconductor between the source electrode and the drain electrode;

depositing a gate insulating film having an opening to the source wire;

forming, on the substrate on which the gate insulating film has been deposited, a second electrode layer, the second electrode layer including;

a gate connection electrode;

a gate wire;

a gate electrode connected to the source wire;

a capacitor wire;

a capacitor electrode connected to the capacitor wire; and

a source connection electrode;

depositing an interlayer insulating film having openings located above the pixel electrode and the opening of the gate insulating film; and

forming a third electrode layer,

the third electrode layer including;

an upper pixel electrode connected to the pixel electrode via a corresponding one of the openings of the interlayer insulating film located above the pixel electrode; and

a connection reinforcement electrode having a stack structure of;

the source wire,

the opening of the gate insulating film,

the source connection electrode, and

a corresponding one of the openings of the interlayer insulating film in this order,

wherein the step of forming the second electrode layer forms the second electrode layer using printing.