THICKER BOTTOM OXIDE FOR REDUCED MILLER CAPACITANCE IN TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)

• US 20150221734A1
• Filed: 02/04/2014
• Published: 08/06/2015
• Est. Priority Date: 08/31/2009
• Status: Abandoned Application

• Current Assignee: Xiaobin Wang, Yeeheng Lee
• Original Assignee: Xiaobin Wang, Yeeheng Lee
• Inventors: Lee, Yeeheng, Wang, Xiaobin
• Application Number:
  US14/171,777
• Publication Number:
  US 20150221734A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor device fabrication method and devices are disclosed. The semiconductor power device is formed on a semiconductor substrate having a plurality of trench transistor cells each having a trench gate. Each of the trench gates having a thicker bottom oxide (TBO) formed by a REOX process on a polysilicon layer deposited on a bottom surface of the trenches.

Claims

1. A semiconductor device formed in a semiconductor substrate comprising:

a trench opened in the semiconductor substrate having a trench bottom surface covered by a first bottom insulation layer and a bottom poly-REOX oxide layer;

the trench further having sidewalls covered by a first sidewall insulation layer and further having a first polysilicon layer covering the first sidewall insulation layer; and

the trench is filled with a second polysilicon layer constituting a trench gate for the semiconductor device.

2. The semiconductor device of claim 1 wherein:

the first bottom insulation layer comprises a first bottom oxide layer and the first sidewall insulation layer comprises a first sidewall oxide layer.

3. The semiconductor device of claim 1 wherein:

the trench has an aspect ratio of trench depth/trench width (B/A)>

3.

4. The semiconductor device of claim 1 wherein:

the first bottom insulation layer and the first sidewall insulation layer having a layer thickness ranging between 50 to 150 Angstroms.

5. The semiconductor device of claim 1 wherein:

the first bottom insulation layer comprises a first bottom oxide layer and the first sidewall insulation layer comprises a first sidewall oxide layer; and

the first bottom oxide layer and the first sidewall oxide layer having a layer thickness ranging between 50 to 150 Angstroms.

6. The semiconductor device of claim 1 wherein:

the bottom poly-REOX oxide layer covering the first bottom insulation layer having a layer thickness ranging between 200 Angstroms to 500 Angstroms.

7. The semiconductor device of claim 1 wherein:

the bottom poly-REOX oxide layer covering the first bottom insulation layer having a greater layer thickness than the sidewall insulation layer.

8. A method for manufacturing a semiconductor device in a semiconductor substrate comprising:

opening a trench in the semiconductor substrate and forming a first insulation layer covering trench sidewalls and a trench bottom surface;

depositing a first polysilicon layer covering over the first insulation layer on the trench bottom surface and the trench sidewalls;

depositing a protective spacer layer covering over the first polysilicon layer on the bottom surface and the trench sidewalls followed by a selective etching to etch the protective spacer layer to expose the first polysilicon layer on the trench bottom surface while covering the first polysilicon layer on trench sidewalls; and

carrying out a poly REOX process for oxidizing the exposed first polysilicon layer on the trench bottom surface forming a poly-REOX layer followed by removing the protective spacer layer from the trench sidewalls and filling the trench with a second polysilicon layer.

9. The method of claim 8 wherein:

the step of opening the trench in the semiconductor substrate comprising a step of forming an oxide-nitride-oxide (ONO) hard mask on top the semiconductor substrate and applying a trench mask to carry out a hard mask etch and a silicon etch to form the trench, the ONO hard mask comprises a bottom oxide layer, a middle nitride layer and a top oxide layer.

10. The method of claim 8 wherein:

the step of forming the protective spacer layer comprising a step of forming a silicon nitride layer.

11. The method of claim 8 wherein:

the step of forming the protective spacer layer comprising a step of forming a silicon nitride layer having a layer thickness ranging between 100 to 300 Angstroms.

12. The method of claim 8 wherein:

the step of forming the first insulation layer comprises a step of forming a first oxide layer to cover the trench bottom surface and the trench sidewalls.

13. The method of claim 8 wherein:

The step of opening the trench comprises a step of opening the trench having an aspect ratio of trench depth/trench width (B/A)>

3.

14. The method of claim 8 wherein:

the step of forming the first insulation layer comprises a step of forming the first insulation layer having a layer thickness ranging between 50 to 150 Angstroms.

15. The method of claim 8 wherein:

the step of forming the first insulation layer further comprises a step of forming the first insulation layer as first oxide layer covering the trench sidewalls and the trench bottom surface having a layer thickness ranging between 50 to 150 Angstroms.

16. The method of claim 8 wherein:

the step of oxidizing the exposed first polysilicon layer form the poly-REOX layer comprises a step of oxidizing the exposed first polysilicon layer on the trench bottom surface to form the poly-REOX layer having a layer thickness ranging between 200 Angstroms to 500 Angstroms.

17. The method of claim 8 wherein:

the step of oxidizing the exposed first polysilicon layer to form the poly-REOX layer comprises a step of oxidizing the exposed first polysilicon layer on the trench bottom surface to form the poly-REOX layer having a greater layer thickness than the sidewall insulation layer.

18. The method of claim 9 further comprising:

performing a chemical-mechanical planarization (CMP) process to planarize the second polysilicon layer to the top surface of the hard mask.

19. The method of claim 18 further comprising:

performing a poly etch back process to etch back the second polysilicon layer to generate a poly-recess and filling the poly-recess with a top oxide layer on top of the second polysilicon layer followed by carrying out a CMP process to planarize the top oxide layer to the top surface of the middle nitride layer of the hard mask.

20. A semiconductor device formed in a semiconductor substrate comprising:

a trench opened in the semiconductor substrate having a thicker trench bottom oxide (TBO) wherein a trench bottom surface covered by a first bottom oxide layer and a bottom poly-REOX oxide layer.