METHOD FOR MANUFACTURING THIN-FILM TRANSISTOR ARRAY SUBSTRATE

• US 20150221753A1
• Filed: 10/17/2013
• Published: 08/06/2015
• Est. Priority Date: 09/30/2013
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Wang, Jun
• Granted Patent: US 9,142,653 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0226 formation by a deposition process per se C23C
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/47573 Etching the layer
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present invention provides a method for manufacturing a thin-film transistor (TFT) array substrate. The TFT array substrate is of a top-gate structure. The method for manufacturing a thin-film transistor array substrate applies three times of masking operation to manufacture the TFT array substrate, wherein IGZO is used to manufacture a TFT of the TFT array substrate so as to greatly increase the charging speed of the TFT with respect to a pixel electrode, improve the response speed of the pixel, and achieve a relatively high refresh rate. Further, the fast response also help improving row scanning rate of pixels to make it possible to achieve ultra-high definition of a TFT LCD. Further, the manufacturing method applies only three times of masking operation so as to significantly reduce the manufacturing steps, shortening the manufacturing time, effectively lowering down the manufacturing cost, and increasing throughput.

Claims

1. A method for manufacturing a thin-film transistor (TFT) array substrate, wherein the TFT array substrate is of a top-gate structure, the method for manufacturing a thin-film transistor comprising the following steps:

(1) providing a substrate;

(2) sequentially depositing and forming a buffer layer, an oxide semiconductor film, and a first metal layer on the substrate;

(3) forming a first photoresist layer on the first metal layer and patterning the first photoresist layer to form, at a predetermined location, a first photoresist pattern, which comprises a first portion and a second portion defining a ditch zone corresponding to the oxide semiconductor film, wherein the first photoresist pattern has a thickness in the second portion that is greater than that of the first portion;

(4) etching off parts of the first metal layer and the oxide semiconductor film that are located in areas not covered by the first photoresist pattern, removing the first portion of the first photoresist pattern to expose the first metal layer, etching off the first metal layer by using the second portion of the first photoresist pattern as a mask in order to expose the oxide semiconductor film, and peeling off the first photoresist pattern in order to form a source terminal and a drain terminal on the first metal layer; and

(5) sequentially depositing an insulation layer and a second metal layer on the substrate and patterning the second metal layer to form a gate terminal.

2. The method for manufacturing a TFT array substrate as claimed in claim 1 further comprising:

a step (6) after step (5) for depositing a protective layer on the substrate, forming a second photoresist layer on the protective layer, and patterning the second photoresist layer to form, at a predetermined location, a second photoresist pattern, which comprises a third portion that is located at one side of the drain terminal and on a portion of the drain terminal and a fourth portion that is located at an opposite side of the drain terminal and on a portion of the drain terminal, wherein the third portion and the fourth portion of the second photoresist pattern define therebetween a recess;

a step (7) after step (6) for etching off a part of the protective layer that is not covered by the second photoresist pattern and a part of the insulation layer corresponding to the part of the protective layer in order to expose the drain terminal, thereby forming a contact hole, and removing the third portion of the second photoresist pattern; and

a step (8) after step (7) for depositing a transparent conductive layer on the substrate and peeling and removing the fourth portion of the second photoresist pattern and the transparent conductive layer located thereon through photoresist peeling.

3. The method for manufacturing a TFT array substrate as claimed in claim 2 further comprising a step (9) after step (8) for subjecting the substrate to an annealing treatment to thus complete the manufacture of the TFT array substrate.

4. The method for manufacturing a TFT array substrate as claimed in claim 1, wherein the substrate comprises a glass substrate;

the buffer layer is formed of deposition of silicon dioxide; and

the oxide semiconductor film comprises an indium gallium zinc oxide (IGZO) film.

5. The method for manufacturing a TFT array substrate as claimed in claim 1, wherein in step (3), the first photoresist pattern is formed by being subjected operations of grey level, masking, exposing, and developing.

6. The method for manufacturing a TFT array substrate as claimed in claim 1, wherein in step (4), a dry etch process is used to etch off the first metal layer with the second portion of the first photoresist pattern as a mask;

and in step (4), peeling off the first photoresist pattern comprises an operation of peeling off the second portion of the first photoresist pattern.

7. The method for manufacturing a TFT array substrate as claimed in claim 1, wherein in step (5), the insulation layer is formed by deposition of silicon dioxide;

and in step (5), the second metal layer is subjected to operations of exposing, developing, etching, and photoresist peeling to form the gate terminal.

8. The method for manufacturing a TFT array substrate as claimed in claim 7, wherein the etching comprises a wet etch process.

9. The method for manufacturing a TFT array substrate as claimed in claim 2, wherein in step (6), the protective layer is formed by deposition of silicon dioxide or silicon nitride;

and the second photoresist pattern is formed by being subjected to grey level, masking, exposing, developing.

10. The method for manufacturing a TFT array substrate as claimed in claim 2, wherein in step (7), a dry etch process is used to etch off the part of the protective layer that is not covered by the second photoresist pattern and the part of the insulation layer corresponding to the part of the protective layer so as to form the contact hole.

11. A method for manufacturing a thin-film transistor (TFT) array substrate, wherein the TFT array substrate is of a top-gate structure, the method for manufacturing a thin-film transistor comprising the following steps:

(1) providing a substrate;

(2) sequentially depositing and forming a buffer layer, an oxide semiconductor film, and a first metal layer on the substrate;

(3) forming a first photoresist layer on the first metal layer and patterning the first photoresist layer to form, at a predetermined location, a first photoresist pattern, which comprises a first portion and a second portion defining a ditch zone corresponding to the oxide semiconductor film, wherein the first photoresist pattern has a thickness in the second portion that is greater than that of the first portion;

(4) etching off parts of the first metal layer and the oxide semiconductor film that are located in areas not covered by the first photoresist pattern, removing the first portion of the first photoresist pattern to expose the first metal layer, etching off the first metal layer by using the second portion of the first photoresist pattern as a mask in order to expose the oxide semiconductor film, and peeling off the first photoresist pattern in order to form a source terminal and a drain terminal on the first metal layer; and

(5) sequentially depositing an insulation layer and a second metal layer on the substrate and patterning the second metal layer to form a gate terminal;

and further comprising;

a step (6) after step (5) for depositing a protective layer on the substrate, forming a second photoresist layer on the protective layer, and patterning the second photoresist layer to form, at a predetermined location, a second photoresist pattern, which comprises a third portion that is located at one side of the drain terminal and on a portion of the drain terminal and a fourth portion that is located at an opposite side of the drain terminal and on a portion of the drain terminal, wherein the third portion and the fourth portion of the second photoresist pattern define therebetween a recess;

a step (7) after step (6) for etching off a part of the protective layer that is not covered by the second photoresist pattern and a part of the insulation layer corresponding to the part of the protective layer in order to expose the drain terminal, thereby forming a contact hole, and removing the third portion of the second photoresist pattern; and

a step (8) after step (7) for depositing a transparent conductive layer on the substrate and peeling and removing the fourth portion of the second photoresist pattern and the transparent conductive layer located thereon through photoresist peeling;

and further comprising a step (9) after step (8) for subjecting the substrate to an annealing treatment to thus complete the manufacture of the TFT array substrate;

wherein the substrate comprises a glass substrate;

the buffer layer is formed of deposition of silicon dioxide; and

the oxide semiconductor film comprises an indium gallium zinc oxide (IGZO) film;

wherein in step (3), the first photoresist pattern is formed by being subjected operations of grey level, masking, exposing, and

developing; and

wherein in step (4), a dry etch process is used to etch off the first metal layer with the second portion of the first photoresist pattern as a mask;

and in step (4), peeling off the first photoresist pattern comprises an operation of peeling off the second portion of the first photoresist pattern.

12. The method for manufacturing a TFT array substrate as claimed in claim 11, wherein in step (5), the insulation layer is formed by deposition of silicon dioxide;

and in step (5), the second metal layer is subjected to operations of exposing, developing, etching, and photoresist peeling to form the gate terminal.

13. The method for manufacturing a TFT array substrate as claimed in claim 12, wherein the etching comprises a wet etch process.

14. The method for manufacturing a TFT array substrate as claimed in claim 11, wherein in step (6), the protective layer is formed by deposition of silicon dioxide or silicon nitride;

and the second photoresist pattern is formed by being subjected to grey level, masking, exposing, developing.

15. The method for manufacturing a TFT array substrate as claimed in claim 11, wherein in step (7), a dry etch process is used to etch off the part of the protective layer that is not covered by the second photoresist pattern and the part of the insulation layer corresponding to the part of the protective layer so as to form the contact hole.