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NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK

  • US 20150221762A1
  • Filed: 04/16/2015
  • Published: 08/06/2015
  • Est. Priority Date: 09/27/2012
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a semiconductor material stack disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region;

    a source and drain material region disposed above the three-dimensional group III-V material body;

    a trench disposed in the source and drain material region separating a source region from a drain region, the trench also disposed in the semiconductor material stack and completely exposing the channel region; and

    a gate stack disposed in the trench and completely surrounding the channel region, the gate stack comprising;

    a first dielectric layer conformal with the trench and disposed on outer portions, but not an inner portion, of the channel region;

    a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of the channel region; and

    a gate electrode disposed on the second dielectric layer.

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