NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK
First Claim
1. A semiconductor device, comprising:
- a semiconductor material stack disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region;
a source and drain material region disposed above the three-dimensional group III-V material body;
a trench disposed in the source and drain material region separating a source region from a drain region, the trench also disposed in the semiconductor material stack and completely exposing the channel region; and
a gate stack disposed in the trench and completely surrounding the channel region, the gate stack comprising;
a first dielectric layer conformal with the trench and disposed on outer portions, but not an inner portion, of the channel region;
a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of the channel region; and
a gate electrode disposed on the second dielectric layer.
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Accused Products
Abstract
Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
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Citations
20 Claims
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1. A semiconductor device, comprising:
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a semiconductor material stack disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region; a source and drain material region disposed above the three-dimensional group III-V material body; a trench disposed in the source and drain material region separating a source region from a drain region, the trench also disposed in the semiconductor material stack and completely exposing the channel region; and a gate stack disposed in the trench and completely surrounding the channel region, the gate stack comprising; a first dielectric layer conformal with the trench and disposed on outer portions, but not an inner portion, of the channel region; a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of the channel region; and a gate electrode disposed on the second dielectric layer. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device, comprising:
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a vertical arrangement of a plurality of group III-V material nanowires disposed above a substrate; a gate stack disposed on and completely surrounding channel regions of each of the group III-V material nanowires, the gate stack comprising; a first dielectric layer disposed on outer portions, but not an inner portion, of each of the channel regions; a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of each of the channel regions; and a gate electrode disposed on the second dielectric layer; a semiconductor layer disposed between the substrate and the bottom-most group III-V material nanowire, wherein a bottom portion of the gate stack is disposed on the semiconductor layer; and source and drain regions disposed in or on each of the group III-V material nanowires, on either side of the gate stack. - View Dependent Claims (7, 8, 9, 10)
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11. A semiconductor device, comprising:
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a semiconductor material stack disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region; a source and drain material region disposed above the three-dimensional group III-V material body; a trench disposed in the source and drain material region separating a source region from a drain region, the trench also disposed in the semiconductor material stack and completely exposing the channel region; and a gate stack disposed in the trench and on and completely surrounding the channel region, the gate stack comprising; a first dielectric layer conformal with the trench and disposed on the exposed portion of the channel region; a second, different, dielectric layer conformal with and disposed on the first dielectric layer, but not on the channel region; and a gate electrode disposed on the second dielectric layer. - View Dependent Claims (12, 13, 14, 15)
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16. A semiconductor device, comprising:
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a vertical arrangement of a plurality of group III-V material nanowires disposed above a substrate; a gate stack disposed on and completely surrounding channel regions of each of the group III-V material nanowires, the gate stack comprising; a first dielectric layer disposed on each of the channel regions; a second, different, dielectric layer conformal with the first dielectric layer and disposed on the first dielectric layer, but not on each of the channel regions; and a gate electrode disposed on the second dielectric layer; source and drain regions disposed in or on each of the group III-V material nanowires, on either side of the gate stack; and a semiconductor layer disposed between the substrate and the bottom-most group III-V material nanowire, wherein a bottom portion of the gate stack is disposed on the semiconductor layer. - View Dependent Claims (17, 18, 19, 20)
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Specification