INTERFACE CIRCUIT OPERATING TO RECOVER ERROR OF TRANSMITTED DATA

• US 20150222389A1
• Filed: 01/09/2015
• Published: 08/06/2015
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Jaegeun, BAE, Joonsung, CHOI, Kwang Hee
• Granted Patent: US 9,515,675 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator

Abstract

Provided is an interface circuit for transmitting and receiving data according to a communication protocol. The interface circuit includes: an encoder configured to encode input data to generate transmission data; a transmitter configured to output the transmission data; a data sequence detector configured to detect whether the number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number; and a recovery section configured to control a recovery operation with respect to the transmission data, based on a detection result of the data sequence detector. With the interface circuit, data loss is prevented and data reliability is guaranteed.

Claims

1. An interface circuit configured to transmit and receive data, the interface circuit comprising:

an encoder configured to encode input data to generate transmission data;

a data sequence detector configured to detect whether a number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number;

a recovery section configured to control, based on a detection result of the data sequence detector, a recovery operation with respect to the transmission data; and

a transmitter configured to output the transmission data.

2. The interface circuit of claim 1, wherein in response to the data sequence detector detecting that the number of the successively same logic values in the data string of the transmission data is equal to or greater than the reference succession number, according to a control of the recovery section, the encoder generates changed transmission data having a different data string from the transmission data by encoding the input data with a different encoding method from an encoding method used when the transmission data is generated, and the transmitter outputs the changed transmission data.

3. The interface circuit of claim 1, wherein in response to the data sequence detector detecting that the number of the successively same logic values in the data string of the transmission data is equal to or greater than the reference succession number, according to a control of the recovery section, the recovery section controls the recovery operation to be performed.

4. The interface circuit of claim 1, wherein in response to the data sequence detector detecting that the number of the successively same logic values in the data string of the transmission data is equal to or greater than the reference succession number, according to a control of the recovery section, one or more bits are inserted into a bit position in a data string of the input data, the encoder encodes the input data together with the inserted one or more bits to generate changed transmission data having a different data string from the transmission data, and the transmitter outputs the changed transmission data.

5. The interface circuit of claim 1, wherein:

the encoder comprises a plurality of encoders; and

the transmitter comprises a plurality of transmitters,

wherein the plurality of encoders are connected to the plurality of transmitters in a one-to-one relationship.

6. The interface circuit of claim 5, wherein:

a first encoder, among the plurality of encoders, encodes the input data to generate first transmission data; and

in response to the data sequence detector detecting that a number of successively same logic values in a data string of the first transmission data is equal to or greater than the reference succession number, according to a control of the recovery section, a second encoder included in the plurality of encoders encodes the input data to generate second transmission data having a different data string from the first transmission data, and one of the plurality of transmitters connected to the second encoder outputs the second transmission data.

7. The interface circuit of claim 1, further comprising:

a recovery number detector configured to detect whether a number of times that the recovery operation is performed is equal to or greater than a reference recovery number,

wherein the recovery section controls the recovery operation with respect to the transmission data, based on the detection result of the data sequence detector and a detection result of the recovery number detector.

8. An interface circuit configured to transmit and receive data according to a peripheral component interconnect express (PCIe) protocol, the interface circuit comprising:

a lane encoder configured to encode input data with a first encoding method of the PCIe protocol to generate transmission data;

a data sequence detector configured to detect whether a number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number;

a link training and status state machine (LTSSM) configured to control, based on a detection result of the data sequence detector, a recovery operation with respect to the transmission data; and

a transmitter configured to output the transmission data.

9. The interface circuit of claim 8, wherein in response to the data sequence detector detecting that the number of the successively same logic values in the data string of the transmission data is equal to or greater than the reference succession number, according to a control of the LTSSM, the lane encoder encodes the input data with a second encoding method of a first generation PCIe protocol or a second generation PCIe protocol, different from the first encoding method, to generate changed transmission data having a different data string from the transmission data, and the transmitter outputs the changed transmission data.

10. The interface circuit of claim 9, wherein after the changed transmission data is output, the lane encoder operates according to a third generation PCIe protocol.

11. The interface circuit of claim 8, wherein in response to the data sequence detector detecting that the number of the successively same logic values in the data string of the transmission data is equal to or greater than the reference succession number, according to a control of the LTSSM, the interface circuit enters a recovery state.

12. The interface circuit of claim 8, wherein in response to the data sequence detector detecting that the number of the successively same logic values in the data string of the transmission data is equal to or greater than the reference succession number, according to a control of the LTSSM, one or more bits are inserted into a bit position in a data string of the input data, the lane encoder encodes the input data together with the inserted one or more bits to generate changed transmission data having a different data string from the transmission data, and the transmitter outputs the changed transmission data.

13. The interface circuit of claim 12, wherein:

the one or more bits are a bit string corresponding to at least one of an idle (IDL) symbol and a data link layer packet (DLLP); and

the one or more bits are inserted into a bit position in front of a first bit of the data string of the input data.

14. The interface circuit of claim 8, wherein:

the lane encoder comprises a plurality of lane encoders;

the transmitter comprises a plurality of transmitters;

the plurality of lane encoders are connected to the plurality of transmitters in a one-to-one relationship;

a first lane encoder included in the plurality of lane encoders encodes the input data to generate first transmission data; and

if a number of successively same logic values in a data string of the first transmission data is equal to or greater than the reference succession number, according to a control of the LTSSM, a second lane encoder included in the plurality of lane encoders encodes the input data to generate second transmission data having a different data string from the first transmission data, and one of the plurality of transmitters connected to the second lane encoder outputs the second transmission data.

15. The interface circuit of claim 8, further comprising:

a recovery number detector configured to detect whether a number of times that the recovery operation is performed is equal to or greater than a reference recovery number,

wherein the LTSSM controls the recovery operation with respect to the transmission data, based on the detection result of the data sequence detector and a detection result of the recovery number detector.

16. A method of generating transmission data, the method comprising:

encoding, by a transmitting device, input data to generate transmission data;

detecting, by the transmitting device, whether a data string of the transmission data sufficiently transits to extract clock information; and

determining, by the transmitting device, whether to perform a recovery operation with respect to the transmission data, based on a result of the detecting.

17. The method of claim 16, wherein the detecting comprises determining whether a number of successively same logic values in the data string of the transmission data is equal to or greater than a reference succession number.

18. The method of claim 16, wherein the determining whether to perform the recovery operation comprises, in response to the result of the detecting determining that the data string of the transmission data does not sufficiently transit to extract clock information, controlling the recovery operation to be performed.

19. The method of claim 18, wherein the controlling the recovery operation to be performed comprises:

encoding the input data with a different encoding method than that performed to generate the transmission data, to generate changed transmission data having a different data string from the transmission data; and

transmitting the changed transmission data.

20. The method of claim 18, wherein the controlling the recovery operation to be performed comprises:

inserting one or more bits into the input data;

encoding the input data including the inserted one or more bits, to generate changed transmission data having a different data string from the transmission data; and

transmitting the changed transmission data.