DEVICE

• US 20150226793A1
• Filed: 02/03/2015
• Published: 08/13/2015
• Est. Priority Date: 02/07/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KUROKAWA, Yoshiyuki
• Granted Patent: US 9,869,716 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 2029/3602 Pattern generator
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only

Abstract

Provided is a device capable of generating test patterns even after the design stage. The area of a circuit which is included in the device and unnecessary during normal operation can be reduced. The device includes a first circuit and a second circuit. The second circuit includes a plurality of third circuits, a plurality of fourth circuits, and a fifth circuit and has a function of generating a signal for testing operation of the first circuit and a function of operating as part of the first circuit. The fourth circuit has a function of storing a first data and a function of storing a second data. The fifth circuit has a function of writing the first data to the plurality of fourth circuits, a function of writing the second data to the plurality of fourth circuits, and a function of reading the second data from the plurality of fourth circuits.

Claims

1. A device comprising:

a first circuit; and

a second circuit comprising;

third circuits;

fourth circuits each comprising a magnetic tunnel junction element; and

a fifth circuit,

wherein the fifth circuit is configured to write first data to the fourth circuits to control conduction between the third circuits in a first period,

wherein the fifth circuit is configured to write second data to the fourth circuits and read the second data from the fourth circuits in a second period, and

wherein the first period is a period of an operation test of the first circuit and the second period is a period in which the operation test of the first circuit is not performed.

2. The device according to claim 1, wherein the fourth circuit is configured to operate as a cache memory of the first circuit in the second period.

3. The device according to claim 1,

wherein the first data are generated in accordance with serial data input to the fifth circuit, and

wherein the second data are generated in accordance with parallel data input to the fifth circuit.

4. The device according to claim 1, wherein the third circuit is configured store data to change a circuit configuration of the third circuit.

5. The device according to claim 1,

wherein the fifth circuit comprises latch circuits,

wherein the first data are input to the fifth circuit through a first wiring one by one,

wherein the second data are input to the fifth circuit through second wirings simultaneously,

wherein the latch circuits are configured to store the first data one by one and store the second data simultaneously, and

wherein the fifth circuit is configured to output the first data to the fourth circuits simultaneously and output the second data to the fourth circuits simultaneously.

6. The device according to claim 1,

wherein the fourth circuit comprises a first transistor and a second transistor electrically connected to the magnetic tunnel junction element,

wherein the first transistor includes a channel formation region in an oxide semiconductor layer, and

wherein the second transistor includes a channel formation region comprising silicon.

7. A device comprising:

a first circuit; and

a second circuit comprising;

third circuits;

fourth circuits each comprising a magnetic tunnel junction element; and

a fifth circuit,

wherein the second circuit is configured to store first data to generate a signal for a testing operation of the first circuit and configured to operate as a memory of the first circuit after the testing operation,

wherein the fifth circuit is configured to write the first data to the fourth circuits to control conduction between the third circuits, and

wherein the fifth circuit is configured to write second data to the fourth circuits and read the second data from the fourth circuits.

8. The device according to claim 7, wherein the fourth circuit is configured to operate as a cache memory of the first circuit after the testing operation.

9. The device according to claim 7,

wherein the first data is generated in accordance with serial data input to the fifth circuit, and

wherein the second data is generated in accordance with parallel data input to the fifth circuit.

10. The device according to claim 7, wherein the third circuit is configured store data to change a circuit configuration of the third circuit.

11. The device according to claim 7,

wherein the fifth circuit comprises latch circuits,

wherein the first data are input to the fifth circuit through a first wiring one by one,

wherein the second data are input to the fifth circuit through second wirings simultaneously,

wherein the latch circuits are configured to store the first data one by one and store the second data simultaneously, and

wherein the fifth circuit is configured to output the first data to the fourth circuits simultaneously and output the second data to the fourth circuits simultaneously.

12. The device according to claim 7,

wherein the fourth circuit comprises a first transistor and a second transistor electrically connected to the magnetic tunnel junction element,

wherein the first transistor includes a channel formation region in an oxide semiconductor layer, and

wherein the second transistor includes a channel formation region comprising silicon.

13. A device comprising:

a first circuit; and

a second circuit comprising a driver circuit and a circuit comprising a magnetic tunnel junction element,

wherein the second circuit is configured to store first data to generate a signal for a testing operation of the first circuit and configured to operate as a memory storing second data of the first circuit after the testing operation,

wherein the first data are input to and stored in the driver circuit one by one and are output from the driver circuit to the circuit simultaneously to reconfigure a circuit configuration of the second circuit, and

wherein the second data are input and stored in the driver circuit simultaneously and are output from the driver circuit to the circuit simultaneously.

14. The device according to claim 13, wherein the circuit comprising the magnetic tunnel junction element is configured to operate as a cache memory of the first circuit after the testing operation.

15. The device according to claim 13,

wherein the driver circuit comprises latch circuits,

wherein the first data are input to the driver circuit through a first wiring one by one,

wherein the second data are input to the driver circuit through second wirings simultaneously,

wherein the latch circuits are configured to store the first data one by one and store the second data simultaneously, and

wherein the driver circuit is configured to output the first data to the circuit simultaneously and output the second data to the circuit simultaneously.

16. The device according to claim 13,

wherein the circuit comprises a first transistor and a second transistor electrically connected to the magnetic tunnel junction element,

wherein the first transistor includes a channel formation region in an oxide semiconductor layer, and

wherein the second transistor includes a channel formation region comprising silicon.