DEVICE

• US 20150226802A1
• Filed: 02/03/2015
• Published: 08/13/2015
• Est. Priority Date: 02/07/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KUROKAWA, Yoshiyuki
• Granted Patent: US 9,983,265 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator

Abstract

Provided is a device capable of generating a new test pattern after the design stage with the area of a circuit that is not in use during normal operation reduced. The device includes a first circuit and a second circuit. The second circuit includes a plurality of third circuits, a plurality of fourth circuits, and a fifth circuit and has a function of generating a signal for testing operation of the first circuit and operating as part of the first circuit. The fourth circuits have a function of storing first data and second data. The fifth circuit has a function of writing the first data to the fourth circuits, writing the second data to the fourth circuits, and reading the second data from the fourth circuits. The first data is used to control the conduction between the third circuits. The second data is used for processing in the first circuit.

Claims

1. A device comprising:

a first circuit; and

a second circuit comprising;

a plurality of third circuits;

a plurality of fourth circuits; and

a fifth circuit,

wherein the second circuit comprises a function of generating a signal for testing operation of the first circuit and a function of operating as part of the first circuit,

wherein the plurality of fourth circuits each comprises a function of storing a first data and a function of storing a second data,

wherein the fifth circuit comprises a function of writing the first data to the plurality of fourth circuits, a function of writing the second data to the plurality of fourth circuits, and a function of reading the second data from the plurality of fourth circuits,

wherein the first data is for controlling the conduction between the plurality of third circuits, and

wherein the second data is used for processing in the first circuit.

2. The device according to claim 1,

wherein the function of operating as part of the first circuit is a function of operating as a cache memory of the first circuit, and

wherein the second data is stored in a memory region of the cache memory

3. The device according to claim 1,

wherein the first data is generated based on a serial data inputted to the fifth circuit, and

wherein the second data is generated based on a parallel data inputted to the fifth circuit.

4. The device according to claim 1,

wherein each of the plurality of fourth circuits comprises a first transistor and a second transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and

wherein the first transistor comprises an oxide semiconductor film comprising a first channel formation region.

5. The device according to claim 4,

wherein the second transistor comprises a second channel formation region comprising silicon.

6. The device according to claim 4,

wherein the oxide semiconductor film comprises indium, gallium, and zinc.

7. The device according to claim 6,

wherein the oxide semiconductor film is a CAAC-OS film.

8. A device comprising:

a first circuit comprising an arithmetic function and a control function; and

a second circuit being reconfigurable, the second circuit comprising;

a plurality of third circuits;

a plurality of fourth circuits; and

a fifth circuit,

wherein the second circuit comprises a function of generating a signal for testing operation of the first circuit and a function of operating as part of the first circuit,

wherein the fifth circuit comprises a function of writing a data for controlling the conduction between the plurality of third circuits to and the plurality of fourth circuits, a function of writing a data used for processing in the first circuit to the plurality of fourth circuits, and a function of reading the data used for processing in the first circuit from the plurality of fourth circuits.

9. The device according to claim 8,

wherein the function of operating as part of the first circuit is a function of operating as a cache memory of the first circuit, and

wherein the data used for processing in the first circuit is stored in a memory region of the cache memory

10. The device according to claim 8,

wherein the data for controlling the conduction between the plurality of third circuits is generated based on a serial data inputted to the fifth circuit, and

wherein the data used for processing in the first circuit is generated based on a parallel data inputted to the fifth circuit.

11. The device according to claim 8,

wherein each of the plurality of fourth circuits comprises a first transistor and a second transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and

wherein the first transistor comprises an oxide semiconductor film comprising a first channel formation region.

12. The device according to claim 11,

wherein the second transistor comprises a second channel formation region comprising silicon.

13. The device according to claim 11

wherein the oxide semiconductor film comprises indium, gallium, and zinc.

14. The device according to claim 13,

wherein the oxide semiconductor film is a CAAC-OS film.

15. A device comprising:

a central processing device comprising a first memory region; and

a reconfiguration circuit configured to be a test circuit, the reconfiguration circuit comprising;

a plurality of logic elements;

a plurality of programmable switches configured to control the conduction between the plurality of logic elements; and

a driver circuit configured to be supplied with a serial data and output a first data to the plurality of programmable switches,

wherein at least parts of the plurality of programmable switches are further configured to be a second memory region,

wherein the driver circuit is further configured to be supplied with a parallel data and output a second data to the second memory region, and

wherein a cache memory comprises the first memory region and the second memory region.

16. The device according to claim 15,

wherein each of the plurality of programmable switches comprises a first transistor and a second transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and

wherein the first transistor comprises an oxide semiconductor film comprising a first channel formation region.

17. The device according to claim 16,

wherein the second transistor comprises a second channel formation region comprising silicon.

18. The device according to claim 16,

wherein the oxide semiconductor film comprises indium, gallium, and zinc.

19. The device according to claim 18,

wherein the oxide semiconductor film is a CAAC-OS film.