DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE

• US 20150227013A1
• Filed: 06/26/2014
• Published: 08/13/2015
• Est. Priority Date: 02/12/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Li, Cheng, Ryu, Bongyeol, Hao, Xueguang, Wei, Xiangdong, Seong Jun, An
• Granted Patent: US 9,354,478 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

Disclosed is a display substrate, including: a substrate; gate lines and data lines arranged in a crisscrossed pattern on the substrate; pixel units surrounded by the gate lines and the data lines, each of which includes a thin film transistor and a pixel electrode; a color filter layer disposed on the substrate and including at least one color region, a vertical projection of the pixel electrode within one of the pixel units on the substrate being within a vertical projection of one color region of the color filter layer on the substrate; and a black matrix disposed over the gate lines, the data lines and the thin film transistors, a vertical projection of all of the gate lines, the data lines and the thin film transistors on the substrate being within a vertical projection of the black matrix on the substrate.

Claims

1. A display substrate, including:

a substrate;

gate lines and data lines arranged in a crisscrossed pattern on the substrate;

pixel units defined by the gate lines and the data lines, each of which includes a thin film transistor and a pixel electrode;

a color filter layer disposed on the substrate and including at least one color region, a vertical projection of the pixel electrode within one of the pixel units on the substrate being within a vertical projection of one color region of the color filter layer on the substrate; and

a black matrix disposed over the gate lines, the data lines and the thin film transistors, a vertical projection of all of the gate lines, the data lines and the thin film transistors on the substrate being within a vertical projection of the black matrix on the substrate.

2. The display substrate according to claim 1, wherein the thin film transistor comprises:

an active layer disposed on the substrate;

a gate insulation layer disposed on the active layer;

a gate disposed on the gate insulation layer;

a source/drain insulation layer disposed on the gate, a first via corresponding to a source and a second via corresponding to a drain being provided in the gate insulation layer and the source/drain insulation layer; and

the source and the drain disposed on the source/drain insulation layer, the source being connected with the active layer through the first via, and the drain being connected with the active layer through the second via.

3. The display substrate according to claim 2, wherein:

the color filter layer is disposed over the source and the drain;

a passivation layer is further provided on the color filter layer on the substrate, and a third via corresponding to the drain and the pixel electrode is provided in the color filter layer and the passivation layer;

the pixel electrode is disposed on the passivation layer and is electrically connected with the drain through the third via; and

the black matrix is disposed over the pixel electrode.

4. The display substrate according to claim 3, wherein:

a common electrode is further provided on the substrate between the color filter layer and the passivation layer; and

a slit is provided in the pixel electrode.

5. The display substrate according to claim 3, wherein:

a common electrode is further provided on the substrate between the color filter layer and the passivation layer; and

the pixel electrode is a strip electrode.

6. The display substrate according to claim 1, wherein:

the black matrix and the color filter layer are disposed in the same layer.

7. A display device, including the display substrate according to claim 1.

8. The display device according to claim 7, wherein the thin film transistor of the display substrate comprises:

an active layer disposed on substrate;

a gate insulation layer disposed on the active layer;

a gate disposed on the gate insulation layer;

a source/drain insulation layer disposed on the gate, a first via corresponding to a source and a second via corresponding to a drain being provided in the gate insulation layer and the source/drain insulation layer; and

the source and the drain disposed on the source/drain insulation layer, the source being connected with the active layer through the first via, and the drain being connected with the active layer through the second via.

9. The display device according to claim 8, wherein:

the color filter layer is disposed over the source and the drain;

a passivation layer is further provided on the color filter layer on the substrate, and a third via corresponding to the drain and the pixel electrode is provided in the color filter layer and the passivation layer;

the pixel electrode is disposed on the passivation layer and is electrically connected with the drain through the third via; and

the black matrix is disposed over the pixel electrode.

10. The display device according to claim 9, wherein:

a common electrode is further provided on the substrate between the color filter layer and the passivation layer; and

a slit is provided in the pixel electrode.

11. The display device according to claim 9, wherein:

a common electrode is further provided on the substrate between the color filter layer and the passivation layer; and

the pixel electrode is a strip electrode.

12. The display device according to claim 7, wherein:

the black matrix and the color filter layer are disposed in the same layer.

13. The display device according to claim 7, wherein:

the display device further includes a bare glass substrate, the bare glass substrate is adapted to be assembled with the display substrate, and liquid crystal is received within a space defined by the bare glass substrate and the display substrate.

14. A method of manufacturing a display substrate, including steps of:

forming, on a substrate, a pattern including gate lines and data lines arranged in a crisscrossed pattern, thin film transistors and pixel electrodes, the thin film transistors and the pixel electrodes being disposed within pixel units defined by the gate lines and the data lines; and

forming patterns of a color filter layer and a black matrix on the substrate,

wherein,

the color filter layer includes at least one color region, and a vertical projection of the pixel electrode within one of the pixel units on the substrate is within a vertical projection of one color region of the color filter layer on the substrate; and

the black matrix is disposed over the gate lines, the data lines and the thin film transistors, and a vertical projection of all of the gate lines, the data lines and the thin film transistors on the substrate is within a vertical projection of the black matrix on the substrate.

15. The method according to claim 14, wherein the step of forming, on the substrate, the pattern including gate lines and data lines arranged in a crisscrossed pattern, thin film transistors and pixel electrodes includes steps of:

forming a semiconductor layer on the substrate, and forming a pattern including an active layer through a patterning process;

forming a gate insulation layer on the substrate on which the pattern of the active layer has been formed;

forming a gate metal layer on the substrate on which the gate insulation layer has been formed, and forming a pattern including the gate lines and gates through a patterning process;

forming a source/drain insulation layer on the substrate on which the pattern of the gate lines and gates have been formed, and forming first vias corresponding to sources and second vias corresponding to drains in the gate insulation layer and the source/drain insulation layer through a patterning process; and

forming a source/drain metal layer on the substrate on which the source/drain insulation layer has been formed, and forming a pattern including the data lines, the sources and the drains through a patterning process, the sources being connected with the active layer through the first vias and the drains being connected with the active layer through the second vias, so that the pattern of the gate lines, the data lines and the thin film transistors is formed.

16. The method according to claim 15, wherein:

the step of forming the pattern of the color filter layer on the substrate includes forming the pattern of the color filter layer on the substrate on which the pattern of the gate lines, the data lines and the thin film transistors has been formed;

the method further includes steps of;

on the substrate on which the pattern of the color filter layer has been formed, forming a passivation layer, and forming a pattern of third vias, which correspond to the drains and the pixel electrodes, on the pattern of the passivation layer and the color filter layer through a patterning process; and

the step of forming, on the substrate, the pattern including gate lines and data lines arranged in a crisscrossed pattern, thin film transistors and pixel electrodes further includes steps of forming a transparent conductive layer on the substrate on which the passivation layer has been formed, and forming a pattern including the pixel electrodes through a patterning process.

17. The method according to claim 16, wherein the step of forming the pattern of the black matrix on the substrate includes steps of:

forming the pattern of the black matrix on the substrate on which the pattern of the pixel electrodes has been formed.

18. The method according to claim 16, further including steps of:

before forming the passivation layer, forming a pattern of a common electrode on the substrate on which the pattern of the color filter layer has been formed, the common electrode being formed between the color filter layer and the passivation layer.

19. The method according to claim 18, wherein after forming the pattern of the common electrode, the method includes steps of:

forming the pattern of the third vias, which correspond to the drains and pixel electrodes, in the common electrode and color filter layer through one patterning process;

forming the passivation layer on the pattern of the common electrode, and then only etching off the passivation layer on bottoms of the third vias with the passivation layer on inner sides of the third vias being remained; and

forming a pattern of pixel electrodes on the passivation layer, pixel electrodes being electrically connected with the drains through the third vias.