CAPACITIVE TOUCH PANEL

• US 20150227233A1
• Filed: 06/11/2014
• Published: 08/13/2015
• Est. Priority Date: 02/10/2014
• Status: Active Grant

• Current Assignee: Quanta Computer
• Original Assignee: Quanta Computer
• Inventors: YI, Chien-Yu, SHEN, Kuo-Liang, CHEN, Ching-Feng
• Granted Patent: US 9,329,742 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/0445 using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G06F 3/0448 Details of the electrode shape, e.g. for enhancing the detection of touches, for generating specific electric field shapes, for enhancing display quality

Abstract

A capacitive touch panel provides a partially high-resolution by mixing multiple resolutions. The capacitive touch panel includes a first electrode layer, a second electrode layer, an insulating layer, and a single one integrated circuit chip. The first electrode layer and the second electrode layer respectively include multiple sensor electrodes disposed with uneven density, so that a part of the touch panel has higher resolution, and other part of the touch panel has lower resolution. The capacitive touch panel provides partially higher resolution by adjusting the distribution of the electrodes without increasing the number of pins of the integrated circuit chip.

Claims

1. A capacitive touch panel, comprising:

a first electrode layer comprising a plurality of first sensing electrode series linearly arranged along a first direction and disconnected from each other, wherein each of the first sensing electrode series comprises a plurality of first sensing electrodes, one portion of the adjacent first sensing electrodes are spaced by a first wide pitch, another portion of the adjacent first sensing electrodes are spaced by a first narrow pitch, and the first wide pitch is longer than the first narrow pitch;

a second electrode layer comprising a plurality of second sensing electrode series linearly arranged along a second direction and disconnected from each other, wherein the first direction is orthogonal to the second direction;

an insulating layer for electrically insulating the first electrode layer from the second electrode layer; and

a single integrated circuit chip comprising a plurality of pins connected to the first sensing electrode series and the second sensing electrode series respectively for detecting a capacitance variation.

2. The capacitive touch panel of claim 1, wherein the integrated circuit chip comprises a plurality of driving pins and a plurality of receiving pins, the driving pins are connected to the first sensing electrode series, the first wide pitch and the first narrow pitch are along the second direction, the first wide pitch is longer than a value of dividing a sensing length of the capacitive touch panel in the second direction to a number of the driving pins, the first narrow pitch is shorter than a value of dividing the sensing length of the capacitive touch panel in the second direction to the number of the driving pins, and the receiving pins are connected to the second sensing electrode series.

3. The capacitive touch panel of claim 1, wherein the integrated circuit chip comprises a plurality of driving pins and a plurality of receiving pins, the driving pins are connected to the first sensing electrode series, the first wide pitch and the first narrow pitch are along the first direction, and the first wide pitch is longer than a value of dividing a sensing length of the capacitive touch panel in the first direction to a number of the receiving pins, the first narrow pitch is shorter than a value of dividing the sensing length of the capacitive touch panel in the first direction to the number of the receiving pins, and the receiving pins are connected to the second sensing electrode series.

4. The capacitive touch panel of claim 1, wherein one portion of the adjacent second sensing electrodes are spaced by a second wide pitch, another portion of the adjacent second sensing electrodes are spaced by a second narrow pitch, and the second wide pitch is longer than the second narrow pitch.

5. The capacitive touch panel of claim 4, wherein the integrated circuit chip comprises a plurality of driving pins and a plurality of receiving pins, the driving pins are connected to the first sensing electrode series, the second wide pitch and the second narrow pitch are along the second direction, the second wide pitch is longer than a value of dividing a sensing length of the capacitive touch panel in the second direction to a number of the driving pins, and the second narrow pitch is shorter than a value of dividing the sensing length of the capacitive touch panel in the second direction to the number of the driving pins.

6. The capacitive touch panel of claim 4, wherein the integrated circuit chip comprises a plurality of driving pins and a plurality of receiving pins, the receiving pins are connected to the second sensing electrode series, the second wide pitch and the second narrow pitch are along the first direction, the second wide pitch is longer than a value of dividing a sensing length of the capacitive touch panel in the first direction to a number of the receiving pins, and the second narrow pitch is shorter than a value of dividing the sensing length of the capacitive touch panel in the first direction to the number of the receiving pins.

7. The capacitive touch panel of claim 4, wherein the second wide pitch is of a length between about 4.5 millimeters and about 6.5 millimeters, and the second narrow pitch is of a length between about 1.5 millimeters and about 2.5 millimeters.

8. The capacitive touch panel of claim 1, wherein the first wide pitch is of a length between about 4.5 millimeters and about 6.5 millimeters, and the first narrow pitch is of a length between about 1.5 millimeters and about 2.5 millimeters.

9. A capacitive touch panel, comprising:

a first electrode layer comprising a first high-density electrode area and a first low-density electrode area;

a second electrode layer comprising a second high-density electrode area and a second low-density electrode area, wherein the first high-density electrode area and the second high-density electrode area are at least partially overlapped and constitute a high-density sensing region, and the first low-density electrode area and the second low-density electrode area are at least partially overlapped and constitute a low-density sensing region;

an insulating layer for electrically insulating the first electrode layer from the second electrode layer; and

a single integrated circuit chip comprising a plurality of pins connected to the first sensing electrode series and the second sensing electrode series respectively for detecting the capacitance variation.

10. The capacitive touch panel of claim 9, wherein a size of a plurality of electrode patterns of the low-density sensing region are larger than a size of a plurality of electrode patterns in the high-density sensing region