SEMICONDUCTOR DEVICE

• US 20150227379A1
• Filed: 02/03/2015
• Published: 08/13/2015
• Est. Priority Date: 02/07/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KUROKAWA, Yoshiyuki
• Granted Patent: US 10,055,232 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A semiconductor device in which the area of a circuit that is not in use during normal operation can be reduced is provided. A semiconductor device including a memory circuit has a function of storing a start-up routine in the memory circuit and executing the start-up routine; a function of operating the memory circuit as a buffer memory device after executing the start-up routine; and a function of loading the start-up routine into the memory circuit from the outside before the semiconductor device is powered off. The memory circuit has a plurality of groups each including at least a first transistor, a second transistor, and a memory element including an MTJ element. The memory element has a function of storing a signal input through the first transistor. The second transistor has a function of being turned on or off in accordance with the signal stored in the memory elements.

Claims

1. A semiconductor device comprising:

a memory circuit,

wherein the semiconductor device is capable of storing a start-up routine in the memory circuit and executing the start-up routine,

wherein the semiconductor device is capable of operating the memory circuit as the buffer memory device after executing the start-up routine,

wherein the semiconductor device is capable of loading the start-up routine into the memory circuit from outside after operating the memory circuit as a buffer memory device and before the semiconductor device is powered off, and

wherein the memory circuit comprises a memory element comprising a magnetic tunnel junction element.

2. The semiconductor device according to claim 1,

wherein the semiconductor device is capable of measuring a length of a period in which a supply of power to the semiconductor device is stopped,

wherein the semiconductor device is capable of comparing the length of the period with a length of a preset period after the supply of power,

wherein the semiconductor device is capable of executing the start-up routine after loading the start-up routine into the memory circuit from outside when the period is longer than the preset period, and

wherein the semiconductor device is capable of executing the start-up routine stored in the memory circuit before the semiconductor device is powered off when the period is shorter than the preset period.

3. The semiconductor device according to claim 1,

wherein the memory circuit further comprises a first transistor, a second transistor, and a third transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the first transistor is electrically connected to a second wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to the magnetic tunnel junction element,

wherein a gate of the second transistor is electrically connected to the magnetic tunnel junction element,

wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a gate of the third transistor is electrically connected to a fourth wiring, and

wherein the other of the source and the drain of the third transistor is electrically connected to a fifth wiring.

4. The semiconductor device according to claim 1,

wherein the memory element further comprises a fourth transistor.

5. The semiconductor device according to claim 1,

wherein at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a channel formation region comprising an oxide semiconductor.

6. An electronic device comprising:

the semiconductor device according to claim 1; and

a housing, a display device, a microphone, or a speaker.

7. A semiconductor device comprising:

a memory circuit,

wherein the semiconductor device is capable of performing a first operation and performing a second operation,

wherein the semiconductor device is capable of being powered off between the first operation and the second operation,

wherein the semiconductor device is capable of storing a start-up routine of the semiconductor device in the memory circuit before the first operation,

wherein the semiconductor device is capable of executing the start-up routine in the first operation,

wherein the semiconductor device is capable of performing an operation based on a setting according to a data stored in the memory circuit in the second operation, and

wherein the memory circuit comprises a memory element comprising a magnetic tunnel junction element.

8. The semiconductor device according to claim 7,

wherein the semiconductor device is capable of measuring a length of a period in which the semiconductor device is powered off,

wherein the semiconductor device is capable of comparing the length of the period with a length of a preset period after a supply of power,

wherein the semiconductor device is capable of executing the start-up routine after loading the start-up routine into the memory circuit from outside when the period is longer than the preset period, and

wherein the semiconductor device is capable of executing the start-up routine stored in the memory circuit before the semiconductor device is powered off when the period is shorter than the preset period.

9. The semiconductor device according to claim 7,

wherein the memory circuit operates as a buffer memory device in the second operation.

10. The semiconductor device according to claim 7, further comprising:

a logic circuit,

wherein the logic circuit comprises a plurality of circuits, and

wherein the memory circuit is capable of controlling electrical connection between the plurality of circuits according to the data.

11. The semiconductor device according to claim 7,

wherein the memory circuit further comprises a first transistor, a second transistor, and a third transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the first transistor is electrically connected to a second wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to the magnetic tunnel junction element,

wherein a gate of the second transistor is electrically connected to the magnetic tunnel junction element,

wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a gate of the third transistor is electrically connected to a fourth wiring, and

wherein the other of the source and the drain of the third transistor is electrically connected to a fifth wiring.

12. The semiconductor device according to claim 7,

wherein the memory element further comprises a fourth transistor.

13. The semiconductor device according to claim 7,

wherein at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a channel formation region comprising an oxide semiconductor.

14. An electronic device comprising:

the semiconductor device according to claim 7; and

a housing, a display device, a microphone, or a speaker.

15. A semiconductor device comprising:

a memory circuit,

wherein the semiconductor device is capable of performing a first operation, being powered off, and then performing a second operation,

wherein the semiconductor device is capable of performing an operation based on a first setting according to a data stored in the memory circuit in the first operation,

wherein the semiconductor device is capable of storing a second setting of the semiconductor device in the memory circuit before the semiconductor device is powered off,

wherein the semiconductor device is capable of executing a program for the second setting of the semiconductor device in the second operation, and

wherein the memory circuit comprises a memory element comprising a magnetic tunnel junction element.

16. The semiconductor device according to claim 15,

wherein the semiconductor device is capable of measuring a length of a period in which the semiconductor device is powered off,

wherein the semiconductor device is capable of comparing the length of the period with a length of a preset period after a supply of power, and

wherein the semiconductor device is capable of executing the program for the second setting of the semiconductor device when the period is shorter than the preset period.

17. The semiconductor device according to claim 15,

wherein the memory circuit operates as a buffer memory device in the first operation.

18. The semiconductor device according to claim 15, further comprising:

a logic circuit,

wherein the logic circuit comprises a plurality of circuits, and

wherein the memory circuit is capable of controlling electrical connection between the plurality of circuits according to the data.

19. The semiconductor device according to claim 15,

wherein the memory circuit further comprises a first transistor, a second transistor, and a third transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the first transistor is electrically connected to a second wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to the magnetic tunnel junction element,

wherein a gate of the second transistor is electrically connected to the magnetic tunnel junction element,

wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a gate of the third transistor is electrically connected to a fourth wiring, and

wherein the other of the source and the drain of the third transistor is electrically connected to a fifth wiring.

20. The semiconductor device according to claim 15,

wherein the memory element further comprises a fourth transistor.

21. The semiconductor device according to claim 15,

wherein at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a channel formation region comprising an oxide semiconductor.

22. An electronic device comprising:

the semiconductor device according to claim 15; and

a housing, a display device, a microphone, or a speaker.