CONFIGURABLE FPGA SOCKETS

• US 20150227662A1
• Filed: 02/13/2015
• Published: 08/13/2015
• Est. Priority Date: 02/13/2014
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Lepercq, Etienne
• Granted Patent: US 9,904,749 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method of emulating a circuit design using an emulator is presented. The method includes allocating one or more spare routing resources to one or more field programmable gate array (FPGA) routing sockets when compiling a plurality of FPGAs disposed in the emulator in preparation for emulating the circuit design, and using the one or more spare routing resources to provide one or more routings among the FPGAs in response to one or more changes made to the circuit design.

Claims

1. A method of emulating a circuit design using an emulator, the method comprising:

allocating one or more spare routing resources to one or more field programmable gate array (FPGA) routing sockets when compiling a plurality of FPGAs disposed in the emulator in preparation for emulating the circuit design; and

using the one or more spare routing resources to provide one or more routings among the FPGAs in response to one or more changes made to the circuit design.

2. The method of claim 1, wherein using the spare routing resources comprises:

recompiling the one or more FPGA routing sockets.

3. The method of claim 1, wherein using the spare routing resources comprises:

directly editing a bitstream image.

4. The method of claim 1, wherein the one or more routings include a route from a first FPGA to a second FPGA.

5. The method of claim 1, wherein the one or more routings include a route from a first portion of a first FPGA to a second portion of the first FPGA, the second portion being different from the first portion.

6. The method of claim 1, wherein the one or more FPGA routing sockets include a first input socket in a first FPGA and a first output socket in the first FPGA, the method comprising using the one or more spare routing resources to provide one or more routings from the first input socket to the first output socket.

7. The method of claim 1, wherein the one or more FPGA routing sockets include a first input socket in a first FPGA and a second input socket in the first FPGA, the method comprising using the one or more spare routing resources to provide one or more routings from the first input socket to the second input socket.

8. The method of claim 1, wherein the one or more FPGA routing sockets include a first input socket in a first FPGA, the method comprising using the one or more spare routing resources to provide one or more routings from the first input socket to the emulated circuit design.

9. The method of claim 1, wherein the one or more FPGA routing sockets include a first output socket in a first FPGA and a first input socket in a second FPGA, the method comprising using the one or more spare routing resources to provide one or more routings from the first output socket to the first input socket.

10. The method of claim 1, wherein allocating includes allocating the one or more spare routing resources for future use during a future compilation of the one or more FPGA routing sockets.

11. The method of claim 10, wherein the one or more spare routing resources are used in response to one or more changes in the circuit design made after the first compilation of the one or more FPGA routing sockets.

12. The method of claim 1, wherein the one or more field programmable gate array (FPGA) routing sockets are not a part of the circuit design.

13. The method of claim 1, wherein the one or more spare routing resources includes one or more spare logic circuits.

14. The method of claim 1, wherein the one or more spare routing resources includes one or more spare interconnects.

15. A system comprising a plurality of field programmable gate arrays (FPGAs) and operative to:

compile the plurality of FPGAs in preparation for emulating a circuit design, while the system is invoked to compile the circuit design;

allocate one or more spare routing resources to one or more FPGA routing sockets; and

use the one or more spare routing resources to provide one or more routings in response to one or more changes made to the circuit design.

16. The system of claim 15, wherein the system is further operative to:

recompile the one or more FPGA routing sockets.

17. The system of claim 15, wherein the system is further operative to:

directly edit a bitstream image.

18. The system of claim 15, wherein the one or more routings include a route from a first FPGA to a second FPGA.

19. The system of claim 15, wherein the one or more routings include a route from a first portion of a first FPGA to a second portion of the first FPGA, the second portion being different from the first portion.

20. The system of claim 15, wherein the one or more FPGA routing sockets include a first input socket in a first FPGA and a first output socket in the first FPGA, wherein the system is further operative to use the one or more spare routing resources to provide one or more routings from the first input socket to the first output socket.

21. The system of claim 15, wherein the one or more FPGA routing sockets include a first input socket in a first FPGA and a second input socket in the first FPGA, wherein the system is further operative to use the one or more spare routing resources to provide one or more routings from the first input socket to the second input socket.

22. The system of claim 15, wherein the one or more FPGA routing sockets include a first input socket in a first FPGA, wherein the system is further operative to use the one or more spare routing resources to provide one or more routings from the first input socket to the emulated circuit design.

23. The system of claim 15, wherein the one or more FPGA routing sockets include a first output socket in a first FPGA and a first input socket in a second FPGA, wherein the system is further operative to use the one or more spare routing resources to provide one or more routings from the first output socket to the first input socket.

24. The system of claim 15, wherein the system is further operative to allocate the one or more spare routing resources for future use during a future compilation of the one or more FPGA routing sockets.

25. The system of claim 24, wherein the system is further operative to use the one or more spare routing resources in response to one or more changes in the circuit design made after the first compilation of the one or more FPGA routing sockets.

26. The system of claim 15, wherein the one or more FPGA routing sockets are not a part of the circuit design.

27. The system of claim 15, wherein the one or more spare routing resources includes one or more spare logic circuits.

28. The system of claim 15, wherein the one or more spare routing resources includes one or more spare interconnects.

29. A non-transitory computer readable storage medium comprising instructions that when executed by a processor cause the processor to:

compile the plurality of FPGAs in preparation for emulating a circuit design, while the system is invoked to compile the circuit design;

allocate one or more spare routing resources to one or more FPGA routing sockets; and

use the one or more spare routing resources to provide one or more routings in response to one or more changes made to the circuit design.

30. The non-transitory computer readable storage medium of claim 29 further comprising instructions to:

recompile the one or more FPGA routing sockets.

31. The non-transitory computer readable storage medium of claim 29 further comprising instructions to:

directly edit a bitstream image.

32. The non-transitory computer readable storage medium of claim 29, wherein the one or more routings include a route from a first FPGA to a second FPGA.

33. The non-transitory computer readable storage medium of claim 29, wherein the one or more routings include a route from a first portion of a first FPGA to a second portion of the first FPGA, the second portion being different from the first portion.

34. The non-transitory computer readable storage medium of claim 29, wherein the one or more FPGA routing sockets include a first input socket in a first FPGA and a first output socket in the first FPGA, wherein the non-transitory computer readable storage medium is further comprising instructions to use the one or more spare routing resources to provide one or more routings from the first input socket to the first output socket.

35. The non-transitory computer readable storage medium of claim 29, wherein the one or more FPGA routing sockets include a first input socket in a first FPGA and a second input socket in the first FPGA, wherein the non-transitory computer readable storage medium is further comprising instructions to use the one or more spare routing resources to provide one or more routings from the first input socket to the second input socket.

36. The non-transitory computer readable storage medium of claim 29, wherein the one or more FPGA routing sockets include a first input socket in a first FPGA, wherein the non-transitory computer readable storage medium is further comprising instructions to provide one or more routings from the first input socket to the emulated circuit design.

37. The non-transitory computer readable storage medium of claim 29, wherein the one or more FPGA routing sockets include a first output socket in a first FPGA and a first input socket in a second FPGA, wherein the non-transitory computer readable storage medium is further comprising instructions to use the one or more spare routing resources to provide one or more routings from the first output socket to the first input socket.

38. The non-transitory computer readable storage medium of claim 29 further comprising instructions to allocate the one or more spare routing resources for future use during a future compilation of the one or more FPGA routing sockets.

39. The non-transitory computer readable storage medium of claim 38 further comprising instructions to use one or more spare routing resources in response to the one or more changes in the circuit design made after the first compilation of the one or more FPGA routing sockets.

40. The non-transitory computer readable storage medium of claim 29, wherein the one or more FPGA routing sockets are not a part of the circuit design.

41. The non-transitory computer readable storage medium of claim 29, wherein the one or more spare routing resources includes one or more spare logic circuits.

42. The non-transitory computer readable storage medium of claim 29, wherein the one or more spare routing resources includes one or more spare interconnects.