CONFIGURABLE FPGA SOCKETS
First Claim
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1. A method of emulating a circuit design using an emulator, the method comprising:
- allocating one or more spare routing resources to one or more field programmable gate array (FPGA) routing sockets when compiling a plurality of FPGAs disposed in the emulator in preparation for emulating the circuit design; and
using the one or more spare routing resources to provide one or more routings among the FPGAs in response to one or more changes made to the circuit design.
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Abstract
A method of emulating a circuit design using an emulator is presented. The method includes allocating one or more spare routing resources to one or more field programmable gate array (FPGA) routing sockets when compiling a plurality of FPGAs disposed in the emulator in preparation for emulating the circuit design, and using the one or more spare routing resources to provide one or more routings among the FPGAs in response to one or more changes made to the circuit design.
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Citations
42 Claims
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1. A method of emulating a circuit design using an emulator, the method comprising:
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allocating one or more spare routing resources to one or more field programmable gate array (FPGA) routing sockets when compiling a plurality of FPGAs disposed in the emulator in preparation for emulating the circuit design; and using the one or more spare routing resources to provide one or more routings among the FPGAs in response to one or more changes made to the circuit design. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A system comprising a plurality of field programmable gate arrays (FPGAs) and operative to:
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compile the plurality of FPGAs in preparation for emulating a circuit design, while the system is invoked to compile the circuit design; allocate one or more spare routing resources to one or more FPGA routing sockets; and use the one or more spare routing resources to provide one or more routings in response to one or more changes made to the circuit design. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A non-transitory computer readable storage medium comprising instructions that when executed by a processor cause the processor to:
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compile the plurality of FPGAs in preparation for emulating a circuit design, while the system is invoked to compile the circuit design; allocate one or more spare routing resources to one or more FPGA routing sockets; and use the one or more spare routing resources to provide one or more routings in response to one or more changes made to the circuit design. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
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Specification