Method For Integrated Circuit Mask Patterning

• US 20150227671A1
• Filed: 02/13/2014
• Published: 08/13/2015
• Est. Priority Date: 02/13/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Ru-Gun, Yu, Jue-Chin, Hsieh, Lun, Chen, Pi-Tsung, Chou, Shuo-Yen
• Granted Patent: US 9,256,709 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Provided is a method of transforming an integrated circuit (IC) pattern into one or more patterns suitable for subsequent processing, such as mask fabrication. The method includes receiving an IC pattern that has an arbitrary shape, and using a computer, deriving an approximation IC pattern, wherein the approximation IC pattern is in a shape that is a user-defined fabrication-friendly shape, such as a rectangle or an ellipse. The method further includes calculating a pattern approximation error between the IC pattern and the approximation IC pattern. The method further includes checking whether the pattern approximation error is less than a user-defined threshold. If it is, the method further includes outputting the approximation IC pattern for subsequent fabrication. Otherwise, the method further includes splitting the IC pattern into a plurality of subparts, and recursively transforming each of the plurality of subparts.

Claims

1. A method of transforming a first integrated circuit (IC) pattern, wherein the first IC pattern includes a shape that is not one of a plurality of user-defined shapes, the method comprising the steps of:

using a computer, deriving a second IC pattern approximating the first IC pattern, wherein the second IC pattern includes a shape that is one of the plurality of user-defined shapes;

calculating a pattern approximation error between the first IC pattern and the second IC pattern; and

upon a condition in which the pattern approximation error is greater than a user-defined threshold, performing the steps of;

splitting the first IC pattern into a plurality of sub-patterns; and

recursively transforming each of the plurality of sub-patterns.

2. The method of claim 1, wherein the first IC pattern includes a plurality of sub-patterns and a plurality of second IC sub-patterns have been derived respectively for the plurality of sub-patterns, further comprising:

connecting the plurality of second IC sub-patterns.

3. The method of claim 1, further comprising, when the pattern approximation error is equal to or less than the user-defined threshold:

outputting the second IC pattern in a computer-readable format.

4. The method of claim 1, wherein the plurality of user-defined shapes includes a rectangle.

5. The method of claim 1, wherein the plurality of user-defined shapes includes an ellipse.

6. The method of claim 1, wherein the second IC pattern has about the same area as the first IC pattern.

7. The method of claim 1, wherein the calculating the pattern approximation error includes:

determining a center of mass of the first IC pattern; and

upon a condition in which the center of mass is outside of the first IC pattern, assigning a value to the pattern approximation error, wherein the value is greater than the user-defined threshold.

8. The method of claim 1, further comprising:

using a computer, determining a center of mass of the first IC pattern; and

upon a condition in which the center of mass is outside of the first IC pattern, performing the steps of;

separating the first IC pattern into a plurality of first IC pattern subsets before the deriving the second IC pattern,

wherein the steps of calculating, deriving, and performing are performed on each of the first IC pattern subsets.

9. The method of claim 1, wherein the deriving the second IC pattern includes:

mapping the first IC pattern to a number (N) of pixels, wherein each of the N pixels has an x-coordinate and an y-coordinate, and is represented by (x_i, y_i) where i∈

[1,N];

calculating an area, a, of the first IC pattern;

calculating a geometric center (x_w,y_w) of the N pixels, wherein

10. The method of claim 1, further comprising:

fabricating a mask with the transformed IC pattern.

11. A method of converting an IC mask pattern that is not a rectangular shape into at least one rectangle for mask fabrication, comprising:

using a computer, determining a rectangle approximating the IC mask pattern, wherein the rectangle and the IC mask pattern share a center of mass;

calculating a pattern approximation error between the rectangle and the IC mask pattern;

when the pattern approximation error is less than a user-defined threshold, accepting the rectangle as a replacement of the IC mask pattern in subsequent mask fabrication,

otherwise,

splitting the IC mask pattern into two subparts; and

recursively converting each of the two subparts that is not already a rectangular shape into at least one rectangle.

12. The method of claim 11, wherein the splitting the IC mask pattern is both along a direction that is in parallel with a shorter side of the rectangle and across the center of mass.

13. The method of claim 11, further comprising:

outputting vertices of the at least one rectangle in a computer-readable format.

14. The method of claim 11, further comprising:

merging the at least one rectangle whereby the merged rectangles approximate the IC mask pattern.

15. The method of claim 11, wherein all sides of the at least one rectangle are oriented along one of two directions:

a first direction and a second direction that is perpendicular to the first direction.

16. The method of claim 11, wherein all sides of the at least one rectangle are oriented along one of four directions:

(1) a first direction, (2) a second direction that is perpendicular to the first direction, (3) a third direction that forms a 45 degree angle with the first direction, and (4) a fourth direction that is perpendicular to the third direction.

17. A method comprising the steps of:

receiving an integrated circuit (IC) design layout, the IC design layout having a first pattern that is not in a rectangular shape;

using a computer, determining a rectangle approximating the first pattern;

calculating a deviation between the first pattern and the rectangle; and

upon a condition in which the deviation is less than a user-defined threshold, replacing the first pattern with the rectangle in the IC design layout,

otherwise, performing the steps of;

splitting the first pattern into a plurality of subparts; and

for each of the plurality of subparts, recursively performing the steps of determining, calculating, conditionally replacing, and conditionally splitting.

18. The method of claim 17, further comprising, when multiple rectangles have thereby been produced for the first pattern:

concatenating the multiple rectangles in the IC design layout in such a way that they collectively approximate the first pattern.

19. The method of claim 17, further comprising:

manufacturing a mask with the IC design layout thus modified; and

exposing a wafer with the mask.

20. The method of claim 17, wherein the splitting step, when executed, produces two subparts.