Computer Hardware Architecture and Data Structures for Packet Binning to Support Incoherent Ray Traversal

• US 20150228051A1
• Filed: 02/13/2014
• Published: 08/13/2015
• Est. Priority Date: 02/13/2014
• Status: Active Grant

• Current Assignee: Alvin D. Zimmerman
• Original Assignee: Raycast Systems, Inc.
• Inventors: Zimmerman, Alvin D.
• Granted Patent: US 9,087,394 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/06 Ray-tracing
• CPC Class Codes: G06T 15/50 Lighting effects
• CPC Class Codes: G06T 2200/04 involving 3D image data
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 2207/10028 Range image; Depth image; 3D point clouds
• CPC Class Codes: G06T 2207/20016 Hierarchical, coarse-to-fine, multiscale or multiresolution image processing; Pyramid transform
• CPC Class Codes: G06T 2207/20021 Dividing image into blocks, subimages or windows
• CPC Class Codes: G06T 2215/12 Shadow map, environment map
• CPC Class Codes: G06T 2215/16 Using real world measurements to influence rendering

Abstract

A new hardware architecture defines an indexing and encoding method for accelerating incoherent ray traversal. Accelerating multiple ray traversal may be accomplished by organizing the rays for minimal movement of data, hiding latency due to external memory access, and performing adaptive binning. Rays may be binned into coarse grain and fine grain spatial bins, independent of direction.

Claims

1. Digital circuitry to create a database of objects in a scene for ray tracing comprising:

a plurality of data arrays in a first memory, each data array corresponding to a cell comprising the scene, each data array operative to receive and store data for objects in the scene that are at least partially contained by the cell corresponding to said each data array;

a plurality of pointer packet registers, each pointer packet register corresponding to a cell comprising the scene and operative to receive and store pointers to areas of memory in a data packet memory separate from the first memory; and

control logic circuitry configured to control operation of the data arrays and pointer packet registers while the data for the objects are being stored in the data arrays, wherein the control logic circuitry;

(i) moves data from a given data array that is on-chip with respect to the digital circuitry into an area of memory in the data packet memory that is off-chip with respect to the digital circuitry when the given data array is in a full condition;

(ii) stores a pointer to the area of memory in the data packet memory into one of the pointer packet registers, wherein said one of the pointer packet registers and the given data array correspond to the same cell; and

(iii) moves data from a given pointer packet register that is on-chip with respect to the digital circuitry into a corresponding pointer packet memory that is off-chip with respect to the digital circuitry when the given pointer packet register is in a full condition,

wherein the control logic circuitry is distributed among the data arrays and the pointer packet registers so that the data arrays operate independently of each other and the pointer packet registers operate independently of each other.

2. The digital circuitry of claim 1 wherein the objects comprise one or more of rays, geometric shapes, or geometric surfaces.

3. The digital circuitry of claim 1 wherein the control logic circuitry is further configured to control operation of the data arrays and pointer packet registers to manage data stored in a plurality of pointer packet memories, wherein the control logic circuitry moves data from each pointer packet memory into one of the data arrays;

and performs (i) to (iii) at the same time that the data from said each pointer packet memory is being stored in the data arrays.

4. The digital circuitry of claim 1 wherein the data for the objects are stored in data arrays according to the cells into which the objects have been binned.

5. The digital circuitry of claim 1 wherein the data packet memory and the pointer packet memory are separate memories.

6. The digital circuitry of claim 1 wherein the data packet memory and the pointer packet memory are the same memory.

8. The digital circuitry of claim 1 wherein the scene is partitioned into a plurality of grids, each grid is partitioned into a plurality of cells.

9. The digital circuitry of claim 1 wherein when the data is moved from the given data array into the corresponding data packet memory, the given data array is reset to accept new data, and when the data is moved from the given pointer packet register into the corresponding pointer packet memory, the given pointer packet register is reset to accept new pointers.

20. The method of claim 1 wherein the pointer packet memory stores data for a plurality of pointers.

21. The digital circuitry of claim 1 wherein (i) and (ii) are performed concurrently.

7. (canceled)

10. Digital circuitry for storing data representative of objects in a scene, the digital circuitry comprising:

a plurality of data arrays in a first memory, each data array corresponding to a cell comprising the scene, each data array operative to receive and store data for objects in the scene that are at least partially contained by the cell corresponding to said each data array;

a plurality of pointer packet registers, each pointer packet register corresponding to a cell comprising the scene and operative to receive and store pointers to areas of memory in a data packet memory separate from the first memory; and

digital circuit means for controlling operation of the data arrays and pointer packet registers while the data for the objects are being stored in the data arrays, including;

(i) moving data from a given data array that is on-chip with respect to the digital circuitry into an area of memory in the data packet memory that is off-chip with respect to the digital circuitry when the given data array is in a full condition;

(ii) storing a pointer to the area of memory in the data packet memory into one of the pointer packet registers, wherein said one of the pointer packet registers and the given data array correspond to the same cell; and

(iii) moving data from a given pointer packet register that is on-chip with respect to the digital circuitry into a pointer packet memory that is off-chip with respect to the digital circuitry when the given pointer packet register is in a full condition,

wherein the digital circuitry means comprises control logic circuitry distributed among the data arrays and the pointer packet registers so that the data arrays operate independently of each other and the pointer packet registers operate independently of each other.

11. The digital circuitry of claim 10 wherein the digital circuitry means further controls operation of the data arrays and pointer packet registers to manage data stored in a plurality of pointer packet memories including moving data from each pointer packet memory into one of the data arrays;

and performing (i) to (iii) while the data from said each pointer packet memory are being stored in the data arrays.

12. The digital circuitry of claim 10 wherein the data for the objects are stored in data arrays according to the cells into which the objects have been binned.

22. The digital circuitry of claim 10 wherein (i) and (ii) are performed concurrently.

13. (canceled)

14. A method in a ray tracing system for creating a database of objects in a scene comprising:

receiving data for objects comprising a scene;

storing the data among a plurality of data arrays in a first memory, each data array corresponding to a cell comprising the scene, each data array operative to receive and store data for objects in the scene that are at least partially contained by the cell corresponding to said each data array;

(i) when a given data array that is on-chip with respect to digital circuitry containing the given data array is in a full condition, then;

logic circuitry causing data to be moved from the given data array into a data packet memory separate from the first memory that is off-chip with respect to the digital circuitry;

the logic circuitry resetting the given data array to accept new data; and

the logic circuitry storing a pointer to the data packet memory into a pointer packet register, from among a plurality of pointer packet registers, that corresponds to the same cell as the given data array; and

(ii) when a given pointer packet register that is on-chip with respect to the digital circuitry is in a full condition, then;

the logic circuitry causing data to be moved from the given pointer packet register into a corresponding pointer packet memory that is off-chip with respect to the digital circuitry; and

the logic circuitry resetting the given pointer packet register to accept new data,

wherein the logic circuitry is distributed among the data packet memory and the pointer packet registers so that the data arrays operate independently of each other and the pointer packet registers operate independently of each other.

15. The method of claim 14 further comprising the logic circuitry moving data from each pointer packet memory into one of the data arrays and performing (i) and (ii) concurrently with the data from said each pointer packet memory being stored in the data arrays.

16. The method of claim 14 wherein the logic circuitry stores the data for the objects in data arrays according to the cells into which the objects have been binned.

17. The method of claim 14 wherein the scene is partitioned into a plurality of grids, each grid is partitioned into a plurality of cells.

18. The method of claim 14 wherein the data packet memory and the pointer packet memory are separate memories.

19. The method of claim 14 wherein the data packet memory and the pointer packet memory are the same memory.

23. The method of claim 14 wherein (i) and (ii) are performed concurrently.