DIMENSION CALCULATION METHOD FOR A SEMICONDUCTOR DEVICE

• US 20150228065A1
• Filed: 02/07/2014
• Published: 08/13/2015
• Est. Priority Date: 02/07/2014
• Status: Active Grant

• Current Assignee: Materials Analysis Technology Inc.
• Original Assignee: Materials Analysis Technology Inc.
• Inventors: BIRING, Sajal
• Granted Patent: US 9,558,565 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06T 2207/10056 Microscopic image
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/12 Edge-based segmentation
• CPC Class Codes: G06T 7/181 involving edge growing; involving edge linking
• CPC Class Codes: G06T 7/62 of area, perimeter, diameter or volume

Abstract

An automatic calculation method for thickness calculation of a deposition layer in a Fin-type field-effect transistor (FinFET) is disclosed through mapping edge lines onto an Excel spreadsheet. The similar method is also applied to the thickness calculation of superlattice or multiple quantum well for a light emitting diode (LED). The edge lines are obtained and transformed from an electronic image taken by Transmission Electron Microscopy (TEM), Focus Ion Beam (FIB), Atomic Force Microscopy (AFM), or X-Ray Diffraction (XRD) of the device.

Claims

1. A dimension calculation method for a semiconductor device, comprises:

image providing;

edge detecting;

noise removing;

edge modifying;

data exporting to Excel spreadsheet; and

data outputting.

2. A dimension calculation method for a semiconductor device as claimed in claim 1, wherein the image is provided by one selected from a group consisting of:

Transmission Electron Microscopy (TEM), Focus Ion Beam (FIB), Atomic Force Microscopy (AFM), and X-Ray Diffraction (XRD).

3. A dimension calculation method for a semiconductor device as claimed in claim 1, wherein the edge detecting is performed by an edge detection filter.

4. A dimension calculation method for a semiconductor device as claimed in claim 3, wherein the edge detection filter is a Gaussian blur and canny algorithm.

5. A dimension calculation method for a semiconductor device as claimed in claim 1, wherein the edge modifying is performed by one software selected from a group consisting of a Polynomial Interpolation and a Linear Interpolation.

6. A dimension calculation method for a semiconductor device as claimed in claim 1, wherein the data outputting is to output one selected from a group consisting of thickness, width, average, deviation, RMS, and Fin angle.

7. A dimension calculation method for a semiconductor device as claimed in claim 1, wherein the semiconductor device is a fin-type field-effect transistor (FinFET).

8. A dimension calculation method for a semiconductor device as claimed in claim 1, wherein the semiconductor device is a Light Emitting Diode (LED), and the image is a superlattice of the device.

9. A dimension calculation method for a semiconductor device as claimed in claim 1, wherein the semiconductor device is a Light Emitting Diode (LED), and the image is a Multiple Quantum Well (MQW) of the device.