Polymer Frame for a Chip, Such That the Frame Comprises at Least One Via in Series with a Capacitor

• US 20150228416A1
• Filed: 11/27/2014
• Published: 08/13/2015
• Est. Priority Date: 08/08/2013
• Status: Active Grant

• Current Assignee: Zhuhai Access Semiconductor Company Limited
• Original Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
• Inventors: Hurwitz, Dror, Huang, Alex
• Granted Patent: US 10,446,335 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01G 17/00 Structural combinations of capacitors or other devices covered by at least two different main groups of this subclass with other electric elements, not covered by this subclass, e.g. RC combinations
• CPC Class Codes: H01G 4/008 Selection of materials
• CPC Class Codes: H01G 4/1209 characterised by the ceramic dielectric material H01G4/1272, H01G4/1281 take precedence
• CPC Class Codes: H01G 4/224 Housing; Encapsulation
• CPC Class Codes: H01G 4/228 Terminals
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/165 : incorporating printed inductors
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2201/09627 : Special connections between adjacent vias, not for grounding vias redundant conductors or connections H05K2201/0979
• CPC Class Codes: H05K 2201/09672 : Superposed layout, i.e. in different planes parallel traces in one plane H05K2201/09236
• CPC Class Codes: H05K 2201/098 : Special shape of the cross-section of conductors, e.g. very thick plated conductors
• CPC Class Codes: H05K 2203/308 : Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
• CPC Class Codes: H05K 3/005 : Punching of holes
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/4647 : by applying an insulating layer around previously made via studs

Abstract

A chip socket defined by an organic matrix framework, wherein the organic matrix framework comprises at least one via post layer where at least one via through the framework around the socket includes at least one capacitor comprising a lower electrode, a dielectric layer and an upper electrode in contact with the via post.

Claims

1. A chip socket defined by an organic matrix framework, wherein the organic matrix framework comprises at least one via post layer where at least one via through a frame around the socket includes at least one capacitor comprising a lower electrode, a dielectric layer and an upper electrode in contact with the via post.

2. The chip socket of claim 1, wherein the dielectric of the capacitor comprises at least one of the group consisting of Ta₂O₅, TiO₂, Ba_xSr_1-x,TiO₃, BaTiO₃, BaO₄SrTi and Al₂O₃.

3. The chip socket of claim 1, wherein the lower electrode of the capacitor comprises a noble metal.

4. The chip socket of claim 1, wherein, the lower electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

5. The chip socket of claim 1, wherein the upper electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

6. The chip socket of claim 1, wherein the at least one via stands on the at least one capacitor.

7. The chip socket of claim 6, wherein the upper electrode comprises the via post.

8. The chip socket of claim 1, wherein the capacitor has a cross-sectional area defined by a cross-sectional area of the via post, that is carefully controlled to tune capacitance of capacitor.

9. The chip socket of claim 1, wherein the at least one capacitor has a capacitance of between 1.5 pF and 300 pF.

10. The chip socket of claim 1, wherein the at least one capacitor has a capacitance of between 5 pF and 45 pF.

11. The chip socket of claim 1 wherein the framework further comprises at least one feature layer.

12. The chip socket of claim 1, wherein at least one electronic component is embedded within the socket and is electrically coupled to the at least one via.

13. The chip socket of claim 1, wherein the at least one electronic component comprises a second capacitor.

14. The chip socket of claim 13, wherein the second capacitor is a discrete component having a metal termination on at least one end.

15. The chip socket of claim 13, wherein the second capacitor is a Metal-Insulator-Metal (MIM) capacitor.

16. The chip socket of claim 13, wherein the Metal-Insulator-Metal (MIM) capacitor comprises a dielectric layer consisting of at least one of the group consisting of Ta₂O₅, TiO₂, Ba_xSr_1-xTiO₃, BaTiO₃, BaO₄SrTi and Al₂O₃.

17. The chip socket of claim 13, wherein a lower electrode of the Metal-Insulator-Metal (MIM) capacitor comprises a noble metal.

18. The chip socket of claim 13, wherein, the lower electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

19. The chip socket of claim 1, wherein an upper electrode of the Metal-Insulator-Metal (MIM) comprises a metal selected from the group consisting of gold, platinum and tantalum.

20. The chip socket of claim 13, wherein the Metal-Insulator-Metal (MIM) capacitor is attached to an insulator carrier.

21. The chip socket of claim 13, wherein the insulator carrier comprises at least one of the group consisting of silicon (Si), SiO₂ (silica), glass, AlN, alumina and c-plane sapphire Al₂O₃ (0001).

22. The chip socket of claim 13, wherein plates of the Metal-Insulator-Metal (MIM) capacitor is coupled to are coupled to vias by feature layers.

23. The chip socket of claim 22, wherein a feature layer on one side of the frame and embedded components comprises an inductor.

24. The chip socket of claim 22 wherein embedded components within the frame, socket and at least one feature within the feature layer provides a filter.

25. The chip socket of claim 22, wherein the filter is selected from the group consisting of basic LC low pass filters, LC high pass filters, LC series band pass filters, LC parallel band pass filters and Low Pass Parallel-Chebyshev filters.

26. The chip socket of claim 1, wherein a chip mounted in a socket is protected from electromagnetic radiation by a Faraday cage comprising via posts within the frame, thereby minimizing electromagnetic interference.

27. The chip socket of claim 26 wherein at least some of the via posts extend in the XY plane.

28. A framework comprising a plurality of sockets for accepting a plurality of chips, wherein each socket comprises a frame and the framework comprises a grid-work of copper via posts and at least one capacitor.

29. The framework of claim 28 wherein a processor chip is embedded in one socket and a passive chip comprising at least one capacitor is embedded in a second socket.

30. A framework comprising a plurality of chip sockets arranged as an array wherein each chip socket is surrounded by a frame.

31. The framework of claim 30, wherein at least one processor chip is embedded in at least one socket.

57. The panel of claim 30 wherein at least one socket is filled with a chip comprising at least one capacitor within a polymer matrix and the framework and chip are thinned to expose ends of vias and connections and terminations are applied by laying down photo-resist on each side of the thinned polymer matrix;

and depositing copper pads into the pattern of photo-resist, the photo-resist is then stripped away and solder mask is laid down between the copper pads, and a protective coating is applied.

32. An array of chip sockets defined by an organic matrix framework of frames surrounding sockets and further comprising a grid of metal via posts through the organic matrix framework wherein at least one via post is coupled in series with at least one capacitor.

33. The array of claim 32 wherein the capacitor comprises a lower electrode, a dielectric layer and is incorporated at a base of the at least one via post, such that the at least one via post stands on the at least one capacitor.

34. The array of claim 32 wherein said at least one via post further comprises an upper electrode of the at least one capacitor.

35. The array of claim 32 wherein the frame comprises at least one feature layer and wherein at least one inductor is formed in the at least one feature layer.

36. The array of claim 32 wherein the organic matrix framework further comprises glass fiber bundles.

37. The array of claim 32 wherein each via is in the range of 25 micron to 500 micron wide.

38. The array of claim 32 wherein each via is cylindrical and has a diameter in the range of 25 micron to 500 micron.

39. The array of claim 32 wherein a frame around at least one socket comprises alternating via posts and feature layers and comprises at least one via post layer and one feature layer.

40. The array of claim 32 wherein, the grid of metal via posts through the organic matrix framework comprises a plurality of via layers.

41. The array of claim 32 wherein a frame around at least one socket comprises a continuous coil of alternating via posts and feature layers spanning at least one via post layer and one feature layer.

42. The array of claim 32 wherein at least one via posts comprises an elongated via post.

43. The array of claim 32 wherein a continuous coil of elongated vias posts spans a plurality of via post layers.

44. The array of claim 32 comprising adjacent chip sockets of different dimensions.

45. The array of claim 43 comprising adjacent chip sockets of different size.

46. The array of claim 42 comprising adjacent chip sockets of different shape.

47. The array of claim 32 wherein the framework comprises at least one feature layer and at least one adjacent via layer, said layers extending in an X-Y plane and having height z, wherein the composite electronic structure comprises at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a lower electrode and a dielectric layer and being incorporated at a base of a via layer sandwiched between the at least one feature layer and a via post, such that the at least one via stands on the at least one capacitor, and optionally forms an upper electrode, wherein the via layer is embedded in a polymer matrix, and

wherein the at least one inductor is formed in at least one of the first feature layer and the adjacent via layer.

48. The array of claim 32 wherein the at least one capacitor and the at least one inductor are coupled in series.

49. The array of claim 32 wherein the frame comprises at least a second feature layer over the via layer, and the at least one capacitor and the at least one inductor are coupled in parallel via the feature layer.

50. The array of claim 49 wherein the at least one inductor is fabricated in the feature layer.

51. The array of claim 32 wherein the at least one inductor is spirally coiled.

52. The array of claim 32 wherein the inductance of the inductor is at least 0.1 nH.

53. The array of claim 32 wherein the inductance is less than 50 nH.

54. The array of claim 32 wherein a further inductor is fabricated in a via layer.

55. The array of claim 54 wherein the inductance of the further inductor is at least 0.1 nH.

56. The array of claim 32 wherein at least one inductor and said at least one capacitor provide a filter selected from the group consisting of basic LC low pass filters, LC high pass filters, LC series band pass filters, LC parallel band pass filters and Low Pass Parallel-Chebyshev filters.

58. A panel comprising an array of chip sockets, each surrounded and defined by an organic matrix framework comprising a grid of copper via posts through the organic matrix framework, wherein said panel comprises at least one region having sockets with a first set of dimensions for receiving one type of chip, and a second region having sockets with a second set of dimensions for receiving a second type of chip and where at least one via post includes a thin film capacitor.

59. The panel of claim 58 wherein the at least one via post stands on the thin film capacitor.

60. The panel of claim 58 wherein the at least one via post comprises an upper electrode of the thin film capacitor.

61. The panel of claim 58 comprising a region with two different socket types in close proximity.