SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20150228538A1
• Filed: 07/28/2014
• Published: 08/13/2015
• Est. Priority Date: 02/11/2014
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: WADA, Makoto, KAJITA, Akihiro, ISOBAYASHI, Atsunobu, SAITO, Tatsuro, ISHIKURA, Taishi
• Application Number:
  US14/444,696
• Publication Number:
  US 20150228538A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

According to one embodiment, a semiconductor device includes a semiconductor substrate, an interlayer insulation film, a plug, a first mark, a second mark, and an upper wiring. The substrate has a device region and a mark formation region. The interlayer insulation film is formed on the substrate. The plug is made of a first metal material in the interlayer insulation film on the device region of the substrate. The first mark is made of the first metal material in the interlayer insulation film on the mark formation region of the substrate. The second mark is made of a second metal material in the interlayer insulation film on the mark formation region of the substrate. The second mark has a concave on a surface thereof. The upper wiring is formed on the interlayer insulation film and is electrically connected to the plug.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a device region and a mark formation region;

an interlayer insulation film on the semiconductor substrate;

a plug made of a first metal material in the interlayer insulation film on the device region of the semiconductor substrate;

a first mark made of the first metal material in the interlayer insulation film on the mark formation region of the semiconductor substrate;

a second mark made of a second metal material in the interlayer insulation film on the mark formation region of the semiconductor substrate and that has a concave on a surface thereof; and

an upper wiring formed on the interlayer insulation film and electrically connected to the plug.

2. The device of claim 1, wherein the first metal material is different from the second metal material.

3. The device of claim 1, wherein the first metal material is same as the second metal material.

4. The device of claim 1, wherein the mark formation region is included in a dicing region of the semiconductor substrate.

5. The device of claim 1, wherein the first and second marks are wider than the plug.

6. The device of claim 1, wherein the plug and the first mark are formed by embedding the first metal material into openings in the interlayer insulation film, respectively.

7. The device of claim 1, wherein the second mark is formed to be along an inner surface of an opening in the interlayer insulation film.

8. The device of claim 1, wherein the upper wiring is made of the second metal material.

9. The device of claim 1, further comprising a protection film that prevents deposition by a CVD method and is formed between the plug and the interlayer insulation film and between the first mark and the interlayer insulation film to cover a side surface of the plug and a side surface of the first mark.

10. The device of claim 1, wherein the semiconductor substrate comprises a lower wiring electrically connected to the plug.

11. A manufacturing method of a semiconductor device, the method comprising:

forming an interlayer insulation film on a semiconductor substrate having a lower wiring;

forming a plug electrically connected to the lower wiring by embedding a first metal material into the interlayer insulation film on a device region of the semiconductor substrate and forming a first mask by embedding the first metal material into the interlayer insulation film on a mark formation region of the semiconductor substrate;

forming a second mark that is made of a second metal material and has a concave on a surface thereof at a predetermined position of the interlayer insulation film on the mark formation region of the semiconductor substrate using the first mark as a reference; and

forming an upper wiring electrically connected to the plug using the second mark as a reference.

12. The method of claim 11, wherein the plug and the first mark are formed by forming openings in the interlayer insulation film and embedding the first metal material into the openings, respectively.

13. The method of claim 11, wherein the plug and the first mark are formed by a reflow PVD method.

14. The method of claim 11, wherein the plug and the first mark are formed by an electroless plating method.

15. The method of claim 12, wherein the plug and the first mark are formed by selectively depositing the first metal material from bottom surfaces of the openings by a CVD method.

16. The method of claim 11, wherein the second mark is formed by forming an opening at a predetermined position of the interlayer insulation film on the mark formation region of the semiconductor substrate using the first mark as a reference and conformally depositing the second metal material on an inner surface of the opening.

17. The method of claim 11, wherein

the upper wiring is formed by

after forming the plug and the first mark,

forming an opening for forming the second mark at a predetermined position of the interlayer insulation film on the mark formation region of the semiconductor substrate using the first mark as a reference,

forming the second mask by depositing the second metal material on an inner surface of the opening and on the interlayer insulation film, and

patterning the second metal material deposited on the interlayer insulation film using the second mark as a reference.

18. The method of claim 11, wherein

the plug and the first mark are formed by

forming openings for forming the plug and the first mark in the interlayer insulation film, respectively,

then forming a protection film preventing deposition by a CVD method on side surfaces of the openings, and

depositing the first metal material from bottom surfaces of the openings by the CVD method.

19. The method of claim 18, wherein

the protection film on the side surfaces of the openings is formed by

after forming the openings for forming the plug and the first mark in the interlayer insulation film,

forming the protection film on inner surfaces of the openings and on the interlayer insulation film, and

removing the protection film formed on the bottom surfaces of the openings.

20. The method of claim 18, wherein

at a time of forming the protection film on inner surfaces of the openings and on the interlayer insulation film,

the protection film is formed to be thicker on a surface of the interlayer insulation film than on the bottom surfaces of the openings.